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https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [tx_dequeue.v] - Diff between revs 25 and 26
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| Rev 25 |
Rev 26 |
| Line 142... |
Line 142... |
reg [63:32] xgxs_txd_barrel;
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reg [63:32] xgxs_txd_barrel;
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reg [7:4] xgxs_txc_barrel;
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reg [7:4] xgxs_txc_barrel;
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reg [63:0] txhfifo_rdata_d1;
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reg [63:0] txhfifo_rdata_d1;
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reg [13:0] add_cnt;
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reg [13:0] byte_cnt;
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reg [13:0] byte_cnt;
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reg [31:0] crc32_d64;
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reg [31:0] crc32_d64;
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reg [31:0] crc32_d8;
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reg [31:0] crc32_d8;
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reg [31:0] crc32_tx;
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reg [31:0] crc32_tx;
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| Line 710... |
Line 711... |
endcase
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endcase
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end
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end
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always @(/*AS*/crc32_d64 or txhfifo_wen or txhfifo_wstatus) begin
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always @(/*AS*/crc32_d64 or next_txhfifo_wstatus or txhfifo_wen
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or txhfifo_wstatus) begin
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if (txhfifo_wen && txhfifo_wstatus[`TXSTATUS_SOP]) begin
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if (txhfifo_wen && txhfifo_wstatus[`TXSTATUS_SOP]) begin
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crc_data = 32'hffffffff;
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crc_data = 32'hffffffff;
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end
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end
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else begin
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else begin
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crc_data = crc32_d64;
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crc_data = crc32_d64;
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end
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end
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if (next_txhfifo_wstatus[`TXSTATUS_EOP] && next_txhfifo_wstatus[2:0] != 3'b0) begin
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add_cnt = {11'b0, next_txhfifo_wstatus[2:0]};
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end
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else begin
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add_cnt = 14'd8;
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end
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end
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end
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always @(/*AS*/byte_cnt or curr_state_pad or txdfifo_rdata
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always @(/*AS*/byte_cnt or curr_state_pad or txdfifo_rdata
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or txdfifo_rempty or txdfifo_ren_d1 or txdfifo_rstatus
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or txdfifo_rempty or txdfifo_ren_d1 or txdfifo_rstatus
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or txhfifo_walmost_full) begin
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or txhfifo_walmost_full) begin
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| Line 891... |
Line 900... |
byte_cnt <= 14'd12;
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byte_cnt <= 14'd12;
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end
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end
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else begin
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else begin
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// if (next_txhfifo_wstatus[`TXSTATUS_EOP] && next_txhfifo_wstatus[2:0] != 3'b0) begin
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byte_cnt <= byte_cnt + add_cnt;
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// byte_cnt <= byte_cnt + {11'b0, next_txhfifo_wstatus[2:0]};
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// end
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// else begin
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byte_cnt <= byte_cnt + 14'd8;
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// end
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end
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end
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frame_end <= next_txhfifo_wstatus[`TXSTATUS_EOP];
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frame_end <= next_txhfifo_wstatus[`TXSTATUS_EOP];
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