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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [tx_enqueue.v] - Diff between revs 7 and 12

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Rev 7 Rev 12
Line 78... Line 78...
reg                     txdfifo_wen;
reg                     txdfifo_wen;
reg [7:0]               txdfifo_wstatus;
reg [7:0]               txdfifo_wstatus;
// End of automatics
// End of automatics
 
 
/*AUTOWIRE*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// End of automatics
 
 
 
 
 
reg             txd_ovflow;
reg             txd_ovflow;
reg             next_txd_ovflow;
reg             next_txd_ovflow;
 
 
Line 123... Line 121...
 
 
always @(/*AS*/pkt_tx_data or pkt_tx_eop or pkt_tx_mod or pkt_tx_sop
always @(/*AS*/pkt_tx_data or pkt_tx_eop or pkt_tx_mod or pkt_tx_sop
         or pkt_tx_val or txd_ovflow or txdfifo_wfull) begin
         or pkt_tx_val or txd_ovflow or txdfifo_wfull) begin
 
 
    txdfifo_wstatus = `TXSTATUS_NONE;
    txdfifo_wstatus = `TXSTATUS_NONE;
    txdfifo_wdata = pkt_tx_data;
 
    txdfifo_wen = pkt_tx_val;
    txdfifo_wen = pkt_tx_val;
 
 
    next_txd_ovflow = txd_ovflow;
    next_txd_ovflow = txd_ovflow;
 
 
 
    `ifdef BIGENDIAN
 
    txdfifo_wdata = {pkt_tx_data[7:0], pkt_tx_data[15:8], pkt_tx_data[23:16], pkt_tx_data[31:24],
 
                     pkt_tx_data[39:32], pkt_tx_data[47:40], pkt_tx_data[55:48],
 
                     pkt_tx_data[63:56]};
 
    `else
 
    txdfifo_wdata = pkt_tx_data;
 
    `endif
 
 
    // Write SOP marker to fifo.
    // Write SOP marker to fifo.
 
 
    if (pkt_tx_val && pkt_tx_sop) begin
    if (pkt_tx_val && pkt_tx_sop) begin
 
 
Line 171... Line 175...
end
end
 
 
 
 
endmodule
endmodule
 
 
 
 
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