| Line 39... |
Line 39... |
`include "defines.v"
|
`include "defines.v"
|
|
|
module xge_mac(/*AUTOARG*/
|
module xge_mac(/*AUTOARG*/
|
// Outputs
|
// Outputs
|
xgmii_txd, xgmii_txc, wb_int_o, wb_dat_o, wb_ack_o, pkt_tx_full,
|
xgmii_txd, xgmii_txc, wb_int_o, wb_dat_o, wb_ack_o, pkt_tx_full,
|
pkt_rx_val, pkt_rx_sop, pkt_rx_err, pkt_rx_eop, pkt_rx_data,
|
pkt_rx_val, pkt_rx_sop, pkt_rx_mod, pkt_rx_err, pkt_rx_eop,
|
pkt_rx_avail,
|
pkt_rx_data, pkt_rx_avail,
|
// Inputs
|
// Inputs
|
xgmii_rxd, xgmii_rxc, wb_we_i, wb_stb_i, wb_rst_i, wb_dat_i,
|
xgmii_rxd, xgmii_rxc, wb_we_i, wb_stb_i, wb_rst_i, wb_dat_i,
|
wb_cyc_i, wb_clk_i, wb_adr_i, reset_xgmii_tx_n, reset_xgmii_rx_n,
|
wb_cyc_i, wb_clk_i, wb_adr_i, reset_xgmii_tx_n, reset_xgmii_rx_n,
|
reset_156m25_n, pkt_tx_val, pkt_tx_sop, pkt_tx_eop, pkt_tx_data,
|
reset_156m25_n, pkt_tx_val, pkt_tx_sop, pkt_tx_mod, pkt_tx_eop,
|
pkt_rx_ren, clk_xgmii_tx, clk_xgmii_rx, clk_156m25
|
pkt_tx_data, pkt_rx_ren, clk_xgmii_tx, clk_xgmii_rx, clk_156m25
|
);
|
);
|
|
|
/*AUTOINPUT*/
|
/*AUTOINPUT*/
|
// Beginning of automatic inputs (from unused autoinst inputs)
|
// Beginning of automatic inputs (from unused autoinst inputs)
|
input clk_156m25; // To rx_dq0 of rx_dequeue.v, ...
|
input clk_156m25; // To rx_dq0 of rx_dequeue.v, ...
|
input clk_xgmii_rx; // To rx_eq0 of rx_enqueue.v, ...
|
input clk_xgmii_rx; // To rx_eq0 of rx_enqueue.v, ...
|
input clk_xgmii_tx; // To tx_dq0 of tx_dequeue.v, ...
|
input clk_xgmii_tx; // To tx_dq0 of tx_dequeue.v, ...
|
input pkt_rx_ren; // To rx_dq0 of rx_dequeue.v
|
input pkt_rx_ren; // To rx_dq0 of rx_dequeue.v
|
input [63:0] pkt_tx_data; // To tx_eq0 of tx_enqueue.v
|
input [63:0] pkt_tx_data; // To tx_eq0 of tx_enqueue.v
|
input [7:0] pkt_tx_eop; // To tx_eq0 of tx_enqueue.v
|
input pkt_tx_eop; // To tx_eq0 of tx_enqueue.v
|
|
input [2:0] pkt_tx_mod; // To tx_eq0 of tx_enqueue.v
|
input pkt_tx_sop; // To tx_eq0 of tx_enqueue.v
|
input pkt_tx_sop; // To tx_eq0 of tx_enqueue.v
|
input pkt_tx_val; // To tx_eq0 of tx_enqueue.v
|
input pkt_tx_val; // To tx_eq0 of tx_enqueue.v
|
input reset_156m25_n; // To rx_dq0 of rx_dequeue.v, ...
|
input reset_156m25_n; // To rx_dq0 of rx_dequeue.v, ...
|
input reset_xgmii_rx_n; // To rx_eq0 of rx_enqueue.v, ...
|
input reset_xgmii_rx_n; // To rx_eq0 of rx_enqueue.v, ...
|
input reset_xgmii_tx_n; // To tx_dq0 of tx_dequeue.v, ...
|
input reset_xgmii_tx_n; // To tx_dq0 of tx_dequeue.v, ...
|
| Line 76... |
Line 77... |
|
|
/*AUTOOUTPUT*/
|
/*AUTOOUTPUT*/
|
// Beginning of automatic outputs (from unused autoinst outputs)
|
// Beginning of automatic outputs (from unused autoinst outputs)
|
output pkt_rx_avail; // From rx_dq0 of rx_dequeue.v
|
output pkt_rx_avail; // From rx_dq0 of rx_dequeue.v
|
output [63:0] pkt_rx_data; // From rx_dq0 of rx_dequeue.v
|
output [63:0] pkt_rx_data; // From rx_dq0 of rx_dequeue.v
|
output [7:0] pkt_rx_eop; // From rx_dq0 of rx_dequeue.v
|
output pkt_rx_eop; // From rx_dq0 of rx_dequeue.v
|
output pkt_rx_err; // From rx_dq0 of rx_dequeue.v
|
output pkt_rx_err; // From rx_dq0 of rx_dequeue.v
|
|
output [2:0] pkt_rx_mod; // From rx_dq0 of rx_dequeue.v
|
output pkt_rx_sop; // From rx_dq0 of rx_dequeue.v
|
output pkt_rx_sop; // From rx_dq0 of rx_dequeue.v
|
output pkt_rx_val; // From rx_dq0 of rx_dequeue.v
|
output pkt_rx_val; // From rx_dq0 of rx_dequeue.v
|
output pkt_tx_full; // From tx_eq0 of tx_enqueue.v
|
output pkt_tx_full; // From tx_eq0 of tx_enqueue.v
|
output wb_ack_o; // From wishbone_if0 of wishbone_if.v
|
output wb_ack_o; // From wishbone_if0 of wishbone_if.v
|
output [31:0] wb_dat_o; // From wishbone_if0 of wishbone_if.v
|
output [31:0] wb_dat_o; // From wishbone_if0 of wishbone_if.v
|
| Line 185... |
Line 187... |
// Outputs
|
// Outputs
|
.rxdfifo_ren (rxdfifo_ren),
|
.rxdfifo_ren (rxdfifo_ren),
|
.pkt_rx_data (pkt_rx_data[63:0]),
|
.pkt_rx_data (pkt_rx_data[63:0]),
|
.pkt_rx_val (pkt_rx_val),
|
.pkt_rx_val (pkt_rx_val),
|
.pkt_rx_sop (pkt_rx_sop),
|
.pkt_rx_sop (pkt_rx_sop),
|
.pkt_rx_eop (pkt_rx_eop[7:0]),
|
.pkt_rx_eop (pkt_rx_eop),
|
.pkt_rx_err (pkt_rx_err),
|
.pkt_rx_err (pkt_rx_err),
|
|
.pkt_rx_mod (pkt_rx_mod[2:0]),
|
.pkt_rx_avail (pkt_rx_avail),
|
.pkt_rx_avail (pkt_rx_avail),
|
.status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog),
|
.status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog),
|
// Inputs
|
// Inputs
|
.clk_156m25 (clk_156m25),
|
.clk_156m25 (clk_156m25),
|
.reset_156m25_n (reset_156m25_n),
|
.reset_156m25_n (reset_156m25_n),
|
| Line 242... |
Line 245... |
.clk_156m25 (clk_156m25),
|
.clk_156m25 (clk_156m25),
|
.reset_156m25_n (reset_156m25_n),
|
.reset_156m25_n (reset_156m25_n),
|
.pkt_tx_data (pkt_tx_data[63:0]),
|
.pkt_tx_data (pkt_tx_data[63:0]),
|
.pkt_tx_val (pkt_tx_val),
|
.pkt_tx_val (pkt_tx_val),
|
.pkt_tx_sop (pkt_tx_sop),
|
.pkt_tx_sop (pkt_tx_sop),
|
.pkt_tx_eop (pkt_tx_eop[7:0]),
|
.pkt_tx_eop (pkt_tx_eop),
|
|
.pkt_tx_mod (pkt_tx_mod[2:0]),
|
.txdfifo_wfull (txdfifo_wfull),
|
.txdfifo_wfull (txdfifo_wfull),
|
.txdfifo_walmost_full(txdfifo_walmost_full));
|
.txdfifo_walmost_full(txdfifo_walmost_full));
|
|
|
tx_dequeue tx_dq0(/*AUTOINST*/
|
tx_dequeue tx_dq0(/*AUTOINST*/
|
// Outputs
|
// Outputs
|
