URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [sim/] [verilog/] [sim.do] - Diff between revs 23 and 24

Rev 23	Rev 24
Line 36...	Line 36...

`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_enqueue.v`	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_enqueue.v`

`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/wishbone_if.v`	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/wishbone_if.v`

	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_stats_fifo.v`

	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_stats_fifo.v`

	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/stats_sm.v`

`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/stats.v`	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/stats.v`

`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/xge_mac.v`	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/xge_mac.v`


Line 86...	Line 92...

`add wave sim:/tb/dut/fault_sm0/*`	`add wave sim:/tb/dut/fault_sm0/*`

`add wave -divider`	`add wave -divider`

`add wave sim:/tb/dut/stats0/*`	`add wave sim:/tb/dut/stats0/stats_sm0/*`

`add wave -divider`	`add wave -divider`

`add wave sim:/tb/dut/wishbone_if0/*`	`add wave sim:/tb/dut/wishbone_if0/*`