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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company: UPT
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// Engineer:
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// Engineer: Constantina-Elena Gavriliu
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//
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//
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// Create Date: 00:31:28 11/19/2013
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// Create Date: 00:31:28 11/19/2013
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// Design Name:
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// Design Name:
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// Module Name: DualPathFPAdder
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// Module Name: DualPathFPAdder
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description: A ± B
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// Description: A ± B
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// //do not take into consideration cases for which the operation generates a NaN or Infinity exception (with corresponding sign) when initial "special cases" are not such exceptions
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//
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//
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// Dependencies:
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// Dependencies: ClosePath.v
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// FarPath.v
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// special_cases.v
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// effective_op.v
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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Line 38... |
parameter pipeline_pos = 0, // 8 bits
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parameter pipeline_pos = 0, // 8 bits
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parameter double_size_mantissa = size_mantissa + size_mantissa,
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parameter double_size_mantissa = size_mantissa + size_mantissa,
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parameter double_size_counter = size_counter + 1,
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parameter double_size_counter = size_counter + 1,
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parameter size = size_mantissa + size_exponent + size_exception_field)
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parameter size = size_mantissa + size_exponent + size_exception_field)
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( input [1:0] conversion,
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( input [size - 1 : 0] a_number_i,
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input sub,
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input [size - 1 : 0] a_number_i,
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input [size - 1 : 0] b_number_i,
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input [size - 1 : 0] b_number_i,
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input sub,
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output[size - 1 : 0] resulted_number_o);
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output[size - 1 : 0] resulted_number_o);
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wire [size_exception_field - 1 : 0] sp_case_a_number, sp_case_b_number;
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wire [size_exception_field - 1 : 0] sp_case_a_number, sp_case_b_number;
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wire [size_mantissa - 1 : 0] m_a_number, m_b_number;
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wire [size_mantissa - 1 : 0] m_a_number, m_b_number;
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wire [size_exponent - 1 : 0] e_a_number, e_b_number;
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wire [size_exponent - 1 : 0] e_a_number, e_b_number;
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wire [size_exponent : 0] exp_inter;
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wire [size_exponent : 0] exp_inter;
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wire [size_mantissa - 1 : 0] shifted_m_b;
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wire [size_mantissa - 1 : 0] shifted_m_b;
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wire [size_mantissa - 1 : 0] initial_rounding_bits, inter_rounding_bits;
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wire [size_mantissa - 1 : 0] initial_rounding_bits, inter_rounding_bits;
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wire eff_op;
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wire eff_op;
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wire [size_mantissa + 1 : 0] adder_mantissa;
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wire [size_mantissa : 0] unnormalized_mantissa;
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wire [size_mantissa : 0] unnormalized_mantissa;
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wire [size_mantissa-1 : 0] fp_resulted_m_o, cp_resulted_m_o;
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wire [size_mantissa-1 : 0] fp_resulted_m_o, cp_resulted_m_o;
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wire [size_exponent-1 : 0] fp_resulted_e_o, cp_resulted_e_o;
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wire [size_exponent-1 : 0] fp_resulted_e_o, cp_resulted_e_o;
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wire [size_exception_field - 1 : 0] resulted_exception_field;
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wire [size_exception_field - 1 : 0] resulted_exception_field;
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wire resulted_sign;
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wire resulted_sign;
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wire swap;
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wire zero_flag;
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wire zero_flag;
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wire [4:0] sign_cases;
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reg intermediar_sign;
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assign e_a_number = a_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
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assign e_a_number = a_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
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assign e_b_number = b_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
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assign e_b_number = b_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
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assign s_a_number = a_number_i[size - size_exception_field - 1];
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assign s_a_number = a_number_i[size - size_exception_field - 1];
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//find the difference between exponents
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//find the difference between exponents
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assign exp_difference = (a_greater_exponent[size_exponent])? b_greater_exponent[size_exponent - 1 : 0] : a_greater_exponent[size_exponent - 1 : 0];
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assign exp_difference = (a_greater_exponent[size_exponent])? b_greater_exponent[size_exponent - 1 : 0] : a_greater_exponent[size_exponent - 1 : 0];
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assign exp_inter = (b_greater_exponent[size_exponent])? {1'b0, e_a_number} : {1'b0, e_b_number};
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assign exp_inter = (b_greater_exponent[size_exponent])? {1'b0, e_a_number} : {1'b0, e_b_number};
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//set shifter always on m_b_number
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//set shifter always on m_b_number
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assign {swap, m_a_number, m_b_number} = (b_greater_exponent[size_exponent])?
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assign {m_a_number, m_b_number} = (b_greater_exponent[size_exponent])?
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{1'b0, {1'b1, a_number_i[size_mantissa - 2 :0]}, {1'b1, b_number_i[size_mantissa - 2 :0]}} :
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{{1'b1, a_number_i[size_mantissa - 2 :0]}, {1'b1, b_number_i[size_mantissa - 2 :0]}} :
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{1'b1, {1'b1, b_number_i[size_mantissa - 2 :0]}, {1'b1, a_number_i[size_mantissa - 2 :0]}};
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{{1'b1, b_number_i[size_mantissa - 2 :0]}, {1'b1, a_number_i[size_mantissa - 2 :0]}};
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effective_op effective_op_instance( .a_sign(s_a_number), .b_sign(s_b_number), .sub(sub), .eff_op(eff_op));
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effective_op effective_op_instance( .a_sign(s_a_number), .b_sign(s_b_number), .sub(sub), .eff_op(eff_op));
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//instantiate FarPath component
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//instantiate FarPath component
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//set zero_flag in case of equal numbers
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//set zero_flag in case of equal numbers
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assign zero_flag = (exp_difference > 1 | !eff_op)?
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assign zero_flag = (exp_difference > 1 | !eff_op)?
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~((|{fp_resulted_m_o, resulted_exception_field[1]}) & (|resulted_exception_field)) :
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~((|{fp_resulted_m_o, resulted_exception_field[1]}) & (|resulted_exception_field)) :
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~((|{cp_resulted_m_o, resulted_exception_field[1]}) & (|resulted_exception_field));
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~((|{cp_resulted_m_o, resulted_exception_field[1]}) & (|resulted_exception_field));
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assign resulted_sign = (exp_difference > 1 | !eff_op)? (!a_greater_exponent[size_exponent]? s_a_number : (eff_op? ~s_b_number : s_b_number)) : (ovf ^ swap);
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assign sign_cases = {eff_op, s_a_number, s_b_number, a_greater_exponent[size_exponent], b_greater_exponent[size_exponent]};
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always
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@(*)
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begin
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case (sign_cases)
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5'b00000: intermediar_sign = 1'b0;
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5'b00001: intermediar_sign = 1'b0;
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5'b00010: intermediar_sign = 1'b0;
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5'b10000: intermediar_sign = ~ovf;
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5'b10001: intermediar_sign = 1'b0;
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5'b10010: intermediar_sign = 1'b1;
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5'b10100: intermediar_sign = ~ovf;
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5'b10101: intermediar_sign = 1'b0;
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5'b10110: intermediar_sign = 1'b1;
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5'b00100: intermediar_sign = 1'b0;
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5'b00101: intermediar_sign = 1'b0;
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5'b00110: intermediar_sign = 1'b0;
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5'b11000: intermediar_sign = ovf;
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5'b11001: intermediar_sign = 1'b1;
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5'b11010: intermediar_sign = 1'b0;
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5'b01000: intermediar_sign = 1'b1;
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5'b01001: intermediar_sign = 1'b1;
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5'b01010: intermediar_sign = 1'b1;
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5'b01100: intermediar_sign = 1'b1;
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5'b01101: intermediar_sign = 1'b1;
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5'b01110: intermediar_sign = 1'b1;
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5'b11100: intermediar_sign = ovf;
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5'b11101: intermediar_sign = 1'b1;
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5'b11110: intermediar_sign = 1'b0;
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default: intermediar_sign = 1'b1;
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endcase
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end
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assign resulted_sign = intermediar_sign;
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assign resulted_number_o = (zero_flag)? {size{1'b0}} :
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assign resulted_number_o = (zero_flag)? {size{1'b0}} :
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(!sp_case_a_number)? {b_number_i[size-1 : size-size_exception_field], eff_op ^ s_b_number, b_number_i[size-1-size_exception_field-1 : 0]} :
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(!sp_case_b_number)? {a_number_i[size-1 : 0]} :
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(exp_difference > 1 | !eff_op)? {resulted_exception_field, resulted_sign, fp_resulted_e_o, fp_resulted_m_o[size_mantissa-2 : 0]}:
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(exp_difference > 1 | !eff_op)? {resulted_exception_field, resulted_sign, fp_resulted_e_o, fp_resulted_m_o[size_mantissa-2 : 0]}:
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{resulted_exception_field, resulted_sign, cp_resulted_e_o, cp_resulted_m_o[size_mantissa-2 : 0]};
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{resulted_exception_field, resulted_sign, cp_resulted_e_o, cp_resulted_m_o[size_mantissa-2 : 0]};
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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