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`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Tubo 8051 cores SPI Interface Module ////`	`//// xSPI Interface Module ////`
`//// ////`	`//// ////`
`//// This file is part of the Turbo 8051 cores project ////`	`//// This file is part of the xspi project ////`
`//// http://www.opencores.org/cores/turbo8051/ ////`	`//// https://opencores.org/projects/xspi ////`
`//// ////`	`//// ////`
`//// Description ////`	`//// Description ////`
`//// Turbo 8051 definitions. ////`	`//// xspi definitions. ////`
`//// ////`	`//// ////`
`//// To Do: ////`	`//// To Do: ////`
`//// nothing ////`	`//// nothing ////`
`//// ////`	`//// ////`
	`//// Version: ////`
	`//// 1.0 - 26th Oct 2019, Initial version ////`
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Dinesh Annayya, dinesha@opencores.org ////`	`//// - Dinesh Annayya, dinesha@opencores.org ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
Line 38...	Line 40...
`//// You should have received a copy of the GNU Lesser General ////`	`//// You should have received a copy of the GNU Lesser General ////`
`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`module spi_core (`	`module xspi_core (`

`clk,`	`clk,`
`reset_n,`	`reset_n,`

`// Reg Bus Interface Signal`	`// Reg Bus Interface Signal`

Line 1...

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  Tubo 8051 cores SPI Interface Module                        ////

////   xSPI Interface Module                                      ////

////                                                              ////

////                                                              ////

////  This file is part of the Turbo 8051 cores project           ////

////  This file is part of the xspi project                       ////

////  http://www.opencores.org/cores/turbo8051/                   ////

////  https://opencores.org/projects/xspi                         ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  Turbo 8051 definitions.                                     ////

////  xspi definitions.                                           ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////    nothing                                                   ////

////    nothing                                                   ////

////                                                              ////

////                                                              ////

////  Version:                                                    ////

////    1.0 - 26th Oct 2019, Initial version                      ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

Line 38...

Line 40...

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

module spi_core (

module xspi_core (

               clk,

               clk,

               reset_n,

               reset_n,

        // Reg Bus Interface Signal

        // Reg Bus Interface Signal

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[/] [xspi/] [trunk/] [rtl/] [xspi/] [xspi_core.v] - Diff between revs 5 and 6