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--
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY ieee;
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USE ieee.STD_LOGIC_1164.ALL;
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USE ieee.NUMERIC_STD.ALL;
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LIBRARY IEEE;
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ENTITY alu IS
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY ALU IS
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PORT (A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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X : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
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SEL : IN STD_LOGIC_VECTOR (5 DOWNTO 0));
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END ALU;
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ARCHITECTURE Behavioral OF ALU IS
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COMPONENT boole IS
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GENERIC (
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GENERIC (
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width : NATURAL := 32);
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (A : IN STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
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PORT(
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B : IN STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
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op : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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X : OUT STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
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A : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SEL : IN STD_LOGIC_VECTOR (2 DOWNTO 0));
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B : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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END COMPONENT boole;
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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FUNCTION alu_add (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION alu_add(
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN -- alu_add
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RETURN STD_LOGIC_VECTOR(UNSIGNED(A) + UNSIGNED(B));
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END alu_add;
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FUNCTION alu_sub (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION alu_sub(
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN -- alu_sub
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RETURN STD_LOGIC_VECTOR(UNSIGNED(A) - UNSIGNED(B));
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END alu_sub;
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FUNCTION alu_inc (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION alu_inc (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN
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RETURN STD_LOGIC_VECTOR(UNSIGNED(A) + 1);
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END alu_inc;
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COMPONENT shift IS
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FUNCTION alu_dec (
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GENERIC (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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width : NATURAL := 16);
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RETURN STD_LOGIC_VECTOR;
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PORT (A : IN STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
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B : IN STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
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FUNCTION alu_dec (
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X : OUT STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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SEL : IN STD_LOGIC_VECTOR (2 DOWNTO 0));
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RETURN STD_LOGIC_VECTOR IS
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END COMPONENT shift;
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BEGIN
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RETURN STD_LOGIC_VECTOR(UNSIGNED(A) - 1);
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COMPONENT addsub IS
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END alu_dec;
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PORT (A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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FUNCTION shift_left (
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SUM : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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CARRY : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
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RETURN STD_LOGIC_VECTOR;
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SEL : IN STD_LOGIC_VECTOR (1 DOWNTO 0));
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END COMPONENT addsub;
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FUNCTION shift_left (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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COMPONENT multiplier IS
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RETURN STD_LOGIC_VECTOR IS
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PORT (A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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BEGIN
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B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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RETURN STD_LOGIC_VECTOR(shift_left(UNSIGNED(A), 1));
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PRODUCT_HIGH : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
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END shift_left;
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PRODUCT_LOW : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
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END COMPONENT multiplier;
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SIGNAL bool_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL shift_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL add_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL carry_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL prod_low_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL prod_high_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
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FUNCTION shift_right (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION shift_right (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN
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BEGIN
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RETURN STD_LOGIC_VECTOR(shift_right(UNSIGNED(A), 1));
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END shift_right;
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END ENTITY alu;
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BOOL1 : boole
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ARCHITECTURE Behavioral OF alu IS
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GENERIC MAP (
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width => 16)
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PORT MAP (
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A => A,
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B => B,
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X => bool_out,
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SEL => SEL(2 DOWNTO 0));
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SHIFT1 : shift PORT MAP (
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A => A,
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B => B,
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X => shift_out,
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SEL => SEL(2 DOWNTO 0));
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ADD1 : addsub PORT MAP (
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A => A,
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B => B,
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SUM => add_out,
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CARRY => carry_out,
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SEL => SEL(1 DOWNTO 0));
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MULT1 : multiplier PORT MAP (
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A => A,
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B => B,
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PRODUCT_HIGH => prod_high_out,
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PRODUCT_LOW => prod_low_out);
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WITH SEL(5 DOWNTO 3) SELECT
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X <=
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bool_out WHEN "000",
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shift_out WHEN "001",
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add_out WHEN "010",
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carry_out WHEN "011",
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prod_low_out WHEN "100",
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prod_high_out WHEN "101",
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X"0000" WHEN OTHERS;
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END Behavioral;
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CONSTANT ZERO : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)
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:= STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data));
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CONSTANT ONE : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)
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:= STD_LOGIC_VECTOR(TO_UNSIGNED(1, w_data));
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BEGIN -- ARCHITECTURE Behavioral
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WITH op SELECT
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y <=
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alu_inc(A) WHEN "0000",
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alu_dec(A) WHEN "0001",
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ZERO WHEN "0010", -- Place holder
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ONE WHEN "0011", -- Place holder
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B WHEN "0100",
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A WHEN "0101", -- Place holder
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A WHEN "0110", -- Place holder
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alu_add(A, B) WHEN "0111",
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alu_sub(A, B) WHEN "1000",
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A WHEN "1001", -- Place holder
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A AND B WHEN "1010",
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A OR B WHEN "1011",
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A XOR B WHEN "1100",
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NOT A WHEN "1101",
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shift_left(A) WHEN "1110",
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shift_right(A) WHEN "1111",
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A WHEN OTHERS;
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END ARCHITECTURE Behavioral;
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No newline at end of file
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No newline at end of file
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