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--
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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-- http://www.gnu.org/licenses/lgpl.txt.
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-- This package is the main interface to the memory. When defining
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-- different sizes, this package generates the main component.
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-- The components themselves are responsible for using the contents
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-- of the passed file name to initialise the memory array.
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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PACKAGE ram_parts IS
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PACKAGE RAM IS
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COMPONENT generic_ram IS
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COMPONENT memory IS
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GENERIC (
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GENERIC (
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filename : STRING := "";
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filename : STRING := "";
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w_data : NATURAL RANGE 1 TO 32 := 16;
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w_data : NATURAL RANGE 1 TO 32 := 16;
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w_addr : NATURAL RANGE 8 TO 14 := 10);
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w_addr : NATURAL RANGE 8 TO 14 := 10);
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| Line 36... |
Line 40... |
a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address
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a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address
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d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
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d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
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q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
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q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
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q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
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q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
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END COMPONENT generic_ram;
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END COMPONENT memory;
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COMPONENT RAM32K IS
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END PACKAGE RAM;
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16;
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file_1 : STRING := "";
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file_2 : STRING := "";
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file_3 : STRING := "";
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file_4 : STRING := "");
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PORT (
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clk : IN STD_LOGIC;
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we : IN STD_LOGIC;
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a1 : IN STD_LOGIC_VECTOR(14 DOWNTO 0); -- Data port address
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a2 : IN STD_LOGIC_VECTOR(14 DOWNTO 0); -- Instruction port address
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d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
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q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
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q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
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END COMPONENT RAM32K;
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END PACKAGE ram_parts;
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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USE std.textio.ALL;
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USE std.textio.ALL;
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USE ieee.std_logic_textio.ALL;
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USE ieee.std_logic_textio.ALL;
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USE work.arrayio.ALL;
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USE work.ram_parts.ALL;
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ENTITY generic_ram IS
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ENTITY memory IS
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-- Memory component based upon Xilinx Spartan-6 block RAM
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-- Memory component based upon Xilinx Spartan-6 block RAM
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-- Maximum capacity is 16k words
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-- Maximum capacity is 16k words
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-- This component can be initialised by passing a file name as a generic
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-- This component can be initialised by passing a file name as a generic
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-- parameter.
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-- parameter.
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GENERIC (
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GENERIC (
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filename : STRING := "";
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filename : STRING := "";
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w_data : NATURAL RANGE 1 TO 32 := 16;
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w_data : NATURAL RANGE 1 TO 32 := 16;
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w_addr : NATURAL RANGE 8 TO 14 := 10);
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w_addr : NATURAL RANGE 8 TO 15 := 10);
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PORT (
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PORT (
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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we : IN STD_LOGIC;
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we : IN STD_LOGIC;
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a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address
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a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address
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a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address
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a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address
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d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
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d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
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q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
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q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
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q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
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q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
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END generic_ram;
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END memory;
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ARCHITECTURE Behavioral OF generic_ram IS
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SIGNAL mem : cstr_array_type(0 TO (2**w_addr) - 1) := init_cstr(2**w_addr, filename);
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SIGNAL address_reg_1 : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);
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SIGNAL address_reg_2 : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);
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BEGIN -- Behavioral
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-- purpose: Try to describe a proper block ram without needing to instantiate a BRAM
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-- type : sequential
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-- inputs : clk, we, a1, a2, d1
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-- outputs: q1, q2
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MP1 : PROCESS (clk, address_reg_1, address_reg_2, mem)
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BEGIN -- PROCESS MP1
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-- Reading
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q1 <= STD_LOGIC_VECTOR(to_unsigned(mem(to_integer(UNSIGNED(address_reg_1))), w_data));
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q2 <= STD_LOGIC_VECTOR(to_unsigned(mem(to_integer(UNSIGNED(address_reg_2))), w_data));
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IF rising_edge(clk) THEN -- rising clock edge
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-- These work like the block RAM registers
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address_reg_1 <= a1;
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address_reg_2 <= a2;
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-- Writing
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IF we = '1' THEN
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mem(to_integer(UNSIGNED(a1))) <= to_integer(UNSIGNED(d1));
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END IF;
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END IF;
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END PROCESS MP1;
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END Behavioral;
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LIBRARY ieee;
|
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE work.mux_parts.ALL;
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USE work.ram_parts.ALL;
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ENTITY RAM32K IS
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ARCHITECTURE Structural OF memory IS
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|
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-- This component is based upon the above defined generic_ram
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-- It is constructed using a 4-to-1 multiplexer and 4 8k word
|
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-- generic_rams.
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-- In order to initialise it, a filename can be passed, which is then
|
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-- used to generate the names of four files which should have been
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-- prepared previously: filename_{0|1|2|3}.txt
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-- These will be used to initialise the four RAM components.
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16;
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file_1 : STRING := "";
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file_2 : STRING := "";
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file_3 : STRING := "";
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file_4 : STRING := "");
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PORT (
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clk : IN STD_LOGIC;
|
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we : IN STD_LOGIC;
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a1 : IN STD_LOGIC_VECTOR(14 DOWNTO 0); -- Data port address
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a2 : IN STD_LOGIC_VECTOR(14 DOWNTO 0); -- Instruction port address
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d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
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q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
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q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
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END RAM32K;
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ARCHITECTURE Structural OF RAM32K IS
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SIGNAL data_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
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SIGNAL data_select : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL instr_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
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SIGNAL instr_select : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL wr_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
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TYPE bus_array_t IS ARRAY(0 TO 3) OF STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL data : bus_array_t;
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SIGNAL inst : bus_array_t;
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|
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TYPE file_array IS ARRAY(INTEGER RANGE <>) OF STRING(1 TO 100);
|
|
|
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CONSTANT i_file : file_array(0 TO 3) := (file_1, file_2, file_3, file_4);
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|
|
|
BEGIN -- Structural
|
BEGIN -- Structural
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|
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data_address <= a1(12 DOWNTO 0);
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SMALL_MEM : IF w_data >= 8 AND w_data <= 14 GENERATE
|
data_select <= a1(14 DOWNTO 13);
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MEM0 : RAM_GENERIC
|
|
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instr_address <= a2(12 DOWNTO 0);
|
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instr_select <= a2(14 DOWNTO 13);
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|
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wr_sel <= "0001" WHEN data_select = "00" AND we = '1' ELSE
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"0010" WHEN data_select = "01" AND we = '1' ELSE
|
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"0100" WHEN data_select = "10" AND we = '1' ELSE
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"1000" WHEN data_select = "11" AND we = '1' ELSE
|
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"0000";
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|
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M1 : mux4to1
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PORT MAP (
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SEL => data_select,
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S0 => data(0),
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S1 => data(1),
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S2 => data(2),
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S3 => data(3),
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Y => q1);
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M2 : mux4to1
|
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PORT MAP (
|
|
SEL => instr_select,
|
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S0 => inst(0),
|
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S1 => inst(1),
|
|
S2 => inst(2),
|
|
S3 => inst(3),
|
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Y => q2);
|
|
|
|
RAM : FOR i IN 0 TO 3 GENERATE
|
|
|
|
R0 : generic_ram
|
|
GENERIC MAP (
|
GENERIC MAP (
|
filename => i_file(i),
|
filename => filename,
|
w_data => w_data,
|
w_data => w_data,
|
w_addr => 13)
|
w_addr => w_addr)
|
PORT MAP (
|
PORT MAP (
|
clk => clk,
|
clk => clk,
|
we => wr_sel(i),
|
we => we,
|
a1 => data_address,
|
a1 => a1,
|
a2 => instr_address,
|
a2 => a2,
|
d1 => d1,
|
d1 => d1,
|
q1 => data(i),
|
q1 => q1,
|
q2 => inst(i));
|
q2 => q2);
|
|
END GENERATE SMALL_MEM;
|
|
|
END GENERATE RAM;
|
LARGE_MEM : IF w_data = 15 GENERATE
|
|
MEM1: RAM32K
|
|
GENERIC MAP (
|
|
filename => filename,
|
|
w_data => w_data)
|
|
PORT MAP (
|
|
clk => clk,
|
|
we => we,
|
|
a1 => a1,
|
|
a2 => a2,
|
|
d1 => d1,
|
|
q1 => q1,
|
|
q2 => q2);
|
|
END GENERATE LARGE_MEM;
|
|
|
END Structural;
|
END Structural;
|
|
|
|
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No newline at end of file
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No newline at end of file
|
