URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [RAM.vhdl] - Diff between revs 17 and 20

Rev 17	Rev 20
Line 30...	Line 30...
`COMPONENT memory IS`	`COMPONENT memory IS`

`GENERIC (`	`GENERIC (`
`filename : STRING := "";`	`filename : STRING := "";`
`w_data : NATURAL RANGE 1 TO 32 := 16;`	`w_data : NATURAL RANGE 1 TO 32 := 16;`
`w_addr : NATURAL RANGE 8 TO 14 := 10);`	`w_addr : NATURAL RANGE 8 TO 15 := 10);`
`PORT (`	`PORT (`
`clk : IN STD_LOGIC;`	`clk : IN STD_LOGIC;`
`we : IN STD_LOGIC;`	`we : IN STD_LOGIC;`
`a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address`	`a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address`
`a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address`	`a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address`