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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE work.mux_parts.ALL;
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-- Proof of concept
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ENTITY ram16kx16 IS
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PORT (
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clk : IN STD_LOGIC;
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we : IN STD_LOGIC;
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a1 : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- Data port address
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a2 : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- Instruction port address
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d1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- Data port input
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q1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- Data port output
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q2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); -- Instruction port output
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END ram16kx16;
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ARCHITECTURE structural OF ram16kx16 IS
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COMPONENT RAM1kx16 IS
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PORT (
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clk : IN STD_LOGIC;
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we : IN STD_LOGIC;
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a1 : IN STD_LOGIC_VECTOR(10 DOWNTO 0); -- Data port address
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a2 : IN STD_LOGIC_VECTOR(10 DOWNTO 0); -- Instruction port address
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d1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- Data port input
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q1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- Data port output
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q2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); -- Instruction port output
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END COMPONENT RAM1kx16;
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SIGNAL data_address : STD_LOGIC_VECTOR(10 DOWNTO 0);
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SIGNAL data_select : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL instr_address : STD_LOGIC_VECTOR(10 DOWNTO 0);
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SIGNAL instr_select : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL wr_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL ds0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ds1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ds2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ds3 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ds4 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ds5 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ds6 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ds7 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL is0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL is1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL is2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL is3 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL is4 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL is5 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL is6 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL is7 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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BEGIN -- structural
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data_address <= a1(10 DOWNTO 0);
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data_select <= a1(13 DOWNTO 11);
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instr_address <= a2(10 DOWNTO 0);
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instr_select <= a2(13 DOWNTO 11);
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WITH data_select SELECT
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wr_sel <=
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"00000001" WHEN "000",
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"00000010" WHEN "001",
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"00000100" WHEN "010",
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"00001000" WHEN "011",
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"00010000" WHEN "100",
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"00100000" WHEN "101",
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"01000000" WHEN "110",
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"10000000" WHEN "111";
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M1 : mux8to1
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PORT MAP (
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SEL => data_select,
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S0 => ds0,
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S1 => ds1,
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S2 => ds2,
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S3 => ds3,
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S4 => ds4,
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S5 => ds5,
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S6 => ds6,
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S7 => ds7,
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Y => q1);
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M2 : mux8to1
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PORT MAP (
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SEL => instr_select,
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S0 => is0,
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S1 => is1,
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S2 => is2,
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S3 => is3,
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S4 => is4,
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S5 => is5,
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S6 => is6,
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S7 => is7,
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Y => q2);
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R0 : RAM1kx16
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PORT MAP (
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clk => clk,
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we => wr_sel(0),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => ds0,
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q2 => is0);
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R1 : RAM1kx16
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PORT MAP (
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clk => clk,
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we => wr_sel(1),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => ds1,
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q2 => is1);
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R2 : RAM1kx16
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PORT MAP (
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clk => clk,
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we => wr_sel(2),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => ds2,
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q2 => is2);
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R3 : RAM1kx16
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PORT MAP (
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clk => clk,
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we => wr_sel(3),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => ds3,
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q2 => is3);
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R4 : RAM1kx16
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PORT MAP (
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clk => clk,
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we => wr_sel(4),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => ds4,
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q2 => is4);
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R5 : RAM1kx16
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PORT MAP (
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clk => clk,
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we => wr_sel(5),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => ds5,
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q2 => is5);
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R6 : RAM1kx16
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PORT MAP (
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clk => clk,
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we => wr_sel(6),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => ds6,
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q2 => is6);
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R7 : RAM1kx16
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PORT MAP (
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clk => clk,
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we => wr_sel(7),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => ds7,
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q2 => is7);
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END structural;
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