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q2 => inst(i));
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q2 => inst(i));
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END GENERATE RAM;
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END GENERATE RAM;
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END Structural;
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END Structural;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE work.mux_parts.ALL;
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USE work.hexio.ALL;
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USE work.ram_parts.all;
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-- Pipelined 32k memory
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ENTITY RAM32K_P IS
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-- This component is based upon the above defined memory
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-- It is constructed using a 4-to-1 multiplexer and 4 8k word
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-- memories.
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16;
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filename : STRING := "");
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PORT (
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clk : IN STD_LOGIC;
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we : IN STD_LOGIC;
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a1 : IN STD_LOGIC_VECTOR(14 DOWNTO 0); -- Data port address
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a2 : IN STD_LOGIC_VECTOR(14 DOWNTO 0); -- Instruction port address
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d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
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q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
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q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
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END RAM32K_P;
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ARCHITECTURE Structural OF RAM32K_P IS
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CONSTANT memory_array : B32K_array_type := init_b32k(filename);
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SIGNAL data_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
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SIGNAL data_select : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL instr_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
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SIGNAL instr_select : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL wr_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
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TYPE bus_array_t IS ARRAY(0 TO 3) OF STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL data : bus_array_t;
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SIGNAL inst : bus_array_t;
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TYPE file_array IS ARRAY(INTEGER RANGE <>) OF STRING(1 TO 100);
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BEGIN -- Structural
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data_address <= a1(12 DOWNTO 0);
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data_select <= a1(14 DOWNTO 13);
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instr_address <= a2(12 DOWNTO 0);
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instr_select <= a2(14 DOWNTO 13);
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wr_sel <= "0001" WHEN data_select = "00" AND we = '1' ELSE
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"0010" WHEN data_select = "01" AND we = '1' ELSE
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"0100" WHEN data_select = "10" AND we = '1' ELSE
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"1000" WHEN data_select = "11" AND we = '1' ELSE
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"0000";
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M1 : mux4to1
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PORT MAP (
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SEL => data_select,
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S0 => data(0),
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S1 => data(1),
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S2 => data(2),
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S3 => data(3),
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Y => q1);
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M2 : mux4to1
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PORT MAP (
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SEL => instr_select,
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S0 => inst(0),
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S1 => inst(1),
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S2 => inst(2),
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S3 => inst(3),
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Y => q2);
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RAM : FOR i IN 0 TO 3 GENERATE
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R0 : generic_memory_block
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GENERIC MAP (
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init_data => memory_array(i),
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w_data => w_data,
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w_addr => 13)
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PORT MAP (
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clk => clk,
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we => wr_sel(i),
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a1 => data_address,
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a2 => instr_address,
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d1 => d1,
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q1 => data(i),
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q2 => inst(i));
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END GENERATE RAM;
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END Structural;
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No newline at end of file
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No newline at end of file
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