| Line 53... |
Line 53... |
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
|
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
|
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
|
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
|
|
|
END COMPONENT RAM32K;
|
END COMPONENT RAM32K;
|
|
|
|
COMPONENT RAM8K IS
|
|
GENERIC (
|
|
initial : cstr_array_type(0 TO 8191);
|
|
w_data : NATURAL RANGE 1 TO 32 := 16);
|
|
PORT (
|
|
clk : IN STD_LOGIC;
|
|
we : IN STD_LOGIC;
|
|
a1 : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
|
a2 : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
|
d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
|
|
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
|
|
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
|
|
END COMPONENT RAM8K;
|
|
|
END PACKAGE ram_parts;
|
END PACKAGE ram_parts;
|
|
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.numeric_std.ALL;
|
USE ieee.numeric_std.ALL;
|
USE std.textio.ALL;
|
USE std.textio.ALL;
|
USE ieee.std_logic_textio.ALL;
|
USE ieee.std_logic_textio.ALL;
|
USE work.arrayio.ALL;
|
USE work.hexio.ALL;
|
|
|
ENTITY RAM_GENERIC IS
|
ENTITY RAM_GENERIC IS
|
|
|
-- Memory component based upon Xilinx Spartan-6 block RAM
|
-- Memory component based upon Xilinx Spartan-6 block RAM
|
-- Maximum capacity is 16k words
|
-- Maximum capacity is 16k words
|
| Line 124... |
Line 138... |
END Behavioral;
|
END Behavioral;
|
|
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.numeric_std.ALL;
|
USE ieee.numeric_std.ALL;
|
|
USE work.hexio.ALL;
|
|
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.ALL;
|
|
USE ieee.numeric_std.ALL;
|
USE work.mux_parts.ALL;
|
USE work.mux_parts.ALL;
|
USE work.ram_parts.ALL;
|
USE work.hexio.ALL;
|
|
|
ENTITY RAM32K IS
|
ENTITY RAM32K IS
|
|
|
-- This component is based upon the above defined memory
|
-- This component is based upon the above defined memory
|
-- It is constructed using a 4-to-1 multiplexer and 4 8k word
|
-- It is constructed using a 4-to-1 multiplexer and 4 8k word
|
| Line 199... |
Line 218... |
S3 => inst(3),
|
S3 => inst(3),
|
Y => q2);
|
Y => q2);
|
|
|
RAM : FOR i IN 0 TO 3 GENERATE
|
RAM : FOR i IN 0 TO 3 GENERATE
|
|
|
R0 : memory
|
R0 : RAM8K
|
GENERIC MAP (
|
GENERIC MAP (
|
filename => i_file(i),
|
filename => i_file(i),
|
w_data => w_data,
|
w_data => w_data)
|
w_addr => 13)
|
|
PORT MAP (
|
PORT MAP (
|
clk => clk,
|
clk => clk,
|
we => wr_sel(i),
|
we => wr_sel(i),
|
a1 => data_address,
|
a1 => data_address,
|
a2 => instr_address,
|
a2 => instr_address,
|
