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[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [ram_parts.vhdl] - Diff between revs 16 and 17

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Rev 16 Rev 17
Line 18... Line 18... 
 
 
 
 
 
 
 
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.numeric_std.ALL;
 
USE ieee.numeric_std.ALL;
 
 
 
USE work.hexio.ALL;
 
 
 
 
 
PACKAGE ram_parts IS
 
PACKAGE ram_parts IS
 
 
 
 
 
  COMPONENT RAM_GENERIC IS
 
  COMPONENT RAM_GENERIC IS
 
    GENERIC (
 
    GENERIC (
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      q1  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);   -- Data port output
 
      q1  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);   -- Data port output
 
      q2  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));  -- Instruction port output
 
      q2  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));  -- Instruction port output
 
 
 
 
 
  END COMPONENT RAM32K;
 
  END COMPONENT RAM32K;
 
 
 
 
 
  COMPONENT RAM8K IS
 
 
 
    GENERIC (
 
 
 
      initial : cstr_array_type(0 TO 8191);
 
 
 
      w_data  : NATURAL RANGE 1 TO 32 := 16);
 
 
 
    PORT (
 
 
 
      clk : IN  STD_LOGIC;
 
 
 
      we  : IN  STD_LOGIC;
 
 
 
      a1  : IN  STD_LOGIC_VECTOR(12 DOWNTO 0);
 
 
 
      a2  : IN  STD_LOGIC_VECTOR(12 DOWNTO 0);
 
 
 
      d1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
 
 
 
      q1  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
 
 
 
      q2  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
 
 
  END COMPONENT RAM8K;
 
 
 
 
 
 
 
END PACKAGE ram_parts;
 
END PACKAGE ram_parts;
 
 
 
 
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.numeric_std.ALL;
 
USE ieee.numeric_std.ALL;
 
USE std.textio.ALL;
 
 
 
USE ieee.std_logic_textio.ALL;
 
 
 
USE work.hexio.ALL;
 
USE work.hexio.ALL;
 
 
 
 
 
ENTITY RAM_GENERIC IS
 
ENTITY RAM_GENERIC IS
 
 
 
 
 
  -- Memory component based upon Xilinx Spartan-6 block RAM
 
  -- Memory component based upon Xilinx Spartan-6 block RAM
Line 138... Line 123... 
END Behavioral;
 
END Behavioral;
 
 
 
 
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.numeric_std.ALL;
 
USE ieee.numeric_std.ALL;
 
USE work.hexio.ALL;
 
 
 
 
 
 
 
LIBRARY ieee;
 
 
 
USE ieee.std_logic_1164.ALL;
 
 
 
USE ieee.numeric_std.ALL;
 
 
 
USE work.mux_parts.ALL;
 
USE work.mux_parts.ALL;
 
USE work.hexio.ALL;
 
USE work.hexio.ALL;
 
 
 
 
 
ENTITY RAM32K IS
 
ENTITY RAM32K IS
 
 
 
 
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END RAM32K;
 
END RAM32K;
 
 
 
 
 
ARCHITECTURE Structural OF RAM32K IS
 
ARCHITECTURE Structural OF RAM32K IS
 
 
 
 
 
 
 
  COMPONENT generic_memory_block IS
 
 
 
 
 
 
 
    GENERIC (
 
 
 
      init_data : cstr_array_type;
 
 
 
      w_data    : NATURAL RANGE 1 TO 32 := 16;
 
 
 
      w_addr    : NATURAL RANGE 8 TO 14 := 10);
 
 
 
    PORT (
 
 
 
      clk : IN  STD_LOGIC;
 
 
 
      we  : IN  STD_LOGIC;
 
 
 
      a1  : IN  STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);  -- Data port address
 
 
 
      a2  : IN  STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);  -- Instruction port address
 
 
 
      d1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);  -- Data port input
 
 
 
      q1  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);  -- Data port output
 
 
 
      q2  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));  -- Instruction port output
 
 
 
 
 
 
 
  END COMPONENT generic_memory_block;
 
 
 
 
 
 
 
  SIGNAL memory_array : B32K_array_type;
 
 
 
 
 
  SIGNAL data_address  : STD_LOGIC_VECTOR(12 DOWNTO 0);
 
  SIGNAL data_address  : STD_LOGIC_VECTOR(12 DOWNTO 0);
 
  SIGNAL data_select   : STD_LOGIC_VECTOR(1 DOWNTO 0);
 
  SIGNAL data_select   : STD_LOGIC_VECTOR(1 DOWNTO 0);
 
  SIGNAL instr_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
 
  SIGNAL instr_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
 
  SIGNAL instr_select  : STD_LOGIC_VECTOR(1 DOWNTO 0);
 
  SIGNAL instr_select  : STD_LOGIC_VECTOR(1 DOWNTO 0);
 
 
 
 
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  SIGNAL data : bus_array_t;
 
  SIGNAL data : bus_array_t;
 
  SIGNAL inst : bus_array_t;
 
  SIGNAL inst : bus_array_t;
 
 
 
 
 
  TYPE file_array IS ARRAY(INTEGER RANGE <>) OF STRING(1 TO 100);
 
  TYPE file_array IS ARRAY(INTEGER RANGE <>) OF STRING(1 TO 100);
 
 
 
 
 
  CONSTANT i_file : file_array(0 TO 3) := (file_1, file_2, file_3, file_4);
 
 
 
 
 
 
 
BEGIN  -- Structural
 
BEGIN  -- Structural
 
 
 
 
 
  data_address <= a1(12 DOWNTO 0);
 
  data_address <= a1(12 DOWNTO 0);
 
  data_select  <= a1(14 DOWNTO 13);
 
  data_select  <= a1(14 DOWNTO 13);
 
 
 
 
Line 218... Line 215... 
      S3  => inst(3),
 
      S3  => inst(3),
 
      Y   => q2);
 
      Y   => q2);
 
 
 
 
 
  RAM : FOR i IN 0 TO 3 GENERATE
 
  RAM : FOR i IN 0 TO 3 GENERATE
 
 
 
 
 
    R0 : RAM8K
 
    R0 : generic_memory_block
 
      GENERIC MAP (
 
      GENERIC MAP (
 
        filename => i_file(i),
 
        init_data => memory_array(i),
 
        w_data   => w_data)
 
        w_data   => w_data,
 
 
 
        w_addr   => 13)
 
      PORT MAP (
 
      PORT MAP (
 
        clk => clk,
 
        clk => clk,
 
        we  => wr_sel(i),
 
        we  => wr_sel(i),
 
        a1  => data_address,
 
        a1  => data_address,
 
        a2  => instr_address,
 
        a2  => instr_address,
Line 235... Line 233... 
 
 
 
 
  END GENERATE RAM;
 
  END GENERATE RAM;
 
 
 
 
 
END Structural;
 
END Structural;
 
 
 
 
 
 
 
 
 
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