| Line 54... |
Line 54... |
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
|
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
|
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
|
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
|
|
|
END COMPONENT RAM32K;
|
END COMPONENT RAM32K;
|
|
|
|
COMPONENT generic_memory_block IS
|
|
|
|
GENERIC (
|
|
init_data : cstr_array_type;
|
|
w_data : NATURAL RANGE 1 TO 32 := 16;
|
|
w_addr : NATURAL RANGE 8 TO 14 := 10);
|
|
PORT (
|
|
clk : IN STD_LOGIC;
|
|
we : IN STD_LOGIC;
|
|
a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address
|
|
a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address
|
|
d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
|
|
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
|
|
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
|
|
|
|
END COMPONENT generic_memory_block;
|
|
|
END PACKAGE ram_parts;
|
END PACKAGE ram_parts;
|
|
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.numeric_std.ALL;
|
USE ieee.numeric_std.ALL;
|
| Line 125... |
Line 142... |
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.numeric_std.ALL;
|
USE ieee.numeric_std.ALL;
|
USE work.mux_parts.ALL;
|
USE work.mux_parts.ALL;
|
USE work.hexio.ALL;
|
USE work.hexio.ALL;
|
|
USE work.ram_parts.all;
|
|
|
ENTITY RAM32K IS
|
ENTITY RAM32K IS
|
|
|
-- This component is based upon the above defined memory
|
-- This component is based upon the above defined memory
|
-- It is constructed using a 4-to-1 multiplexer and 4 8k word
|
-- It is constructed using a 4-to-1 multiplexer and 4 8k word
|
| Line 148... |
Line 166... |
|
|
END RAM32K;
|
END RAM32K;
|
|
|
ARCHITECTURE Structural OF RAM32K IS
|
ARCHITECTURE Structural OF RAM32K IS
|
|
|
COMPONENT generic_memory_block IS
|
|
|
|
GENERIC (
|
|
init_data : cstr_array_type;
|
|
w_data : NATURAL RANGE 1 TO 32 := 16;
|
|
w_addr : NATURAL RANGE 8 TO 14 := 10);
|
|
PORT (
|
|
clk : IN STD_LOGIC;
|
|
we : IN STD_LOGIC;
|
|
a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address
|
|
a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address
|
|
d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input
|
|
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output
|
|
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output
|
|
|
|
END COMPONENT generic_memory_block;
|
|
|
|
SIGNAL memory_array : B32K_array_type;
|
SIGNAL memory_array : B32K_array_type;
|
|
|
SIGNAL data_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
|
SIGNAL data_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
|
SIGNAL data_select : STD_LOGIC_VECTOR(1 DOWNTO 0);
|
SIGNAL data_select : STD_LOGIC_VECTOR(1 DOWNTO 0);
|
SIGNAL instr_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
|
SIGNAL instr_address : STD_LOGIC_VECTOR(12 DOWNTO 0);
|
