URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [tb_generic_ram.vhdl] - Diff between revs 5 and 17

Rev 5	Rev 17
Line 42...	Line 42...

`SIGNAL ctr_a : NATURAL RANGE 0 TO (2**w_addr - 1);`	`SIGNAL ctr_a : NATURAL RANGE 0 TO (2**w_addr - 1);`

`BEGIN -- ARCHITECTURE Structural`	`BEGIN -- ARCHITECTURE Structural`

`RAM1 : generic_ram`	`RAM1 : RAM_GENERIC`
`GENERIC MAP (`	`GENERIC MAP (`
`filename => "test_data.txt",`	`filename => "test_data.txt",`
`w_addr => 12)`	`w_addr => 12)`
`PORT MAP (`	`PORT MAP (`
`clk => clock,`	`clk => clock,`