Subversion Repositories xucpu

LIBRARY ieee;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

USE ieee.numeric_std.ALL;

-- Test bench for instatiating a memory and initialising

-- Test bench for instatiating a memory and initialising

-- it from a file.

-- it from a file.

ENTITY tb_generic_ram IS

ENTITY tb_generic_ram IS

END ENTITY tb_generic_ram;

END ENTITY tb_generic_ram;

ARCHITECTURE Structural OF tb_generic_ram IS

ARCHITECTURE Structural OF tb_generic_ram IS

  SIGNAL clock  : STD_LOGIC                             := '0';

  SIGNAL clock  : STD_LOGIC                             := '0';

  SIGNAL we     : STD_LOGIC                             := '0';

  SIGNAL we     : STD_LOGIC                             := '0';

  SIGNAL data_a : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0) := (OTHERS => '0');

  SIGNAL data_a : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0) := (OTHERS => '0');

  SIGNAL inst_a : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);

  SIGNAL inst_a : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);

  SIGNAL ctr_a : NATURAL RANGE 0 TO (2**w_addr - 1);

  SIGNAL ctr_a : NATURAL RANGE 0 TO (2**w_addr - 1);

BEGIN  -- ARCHITECTURE Structural

BEGIN  -- ARCHITECTURE Structural

    GENERIC MAP (

    GENERIC MAP (

      filename => "test_data.txt",

      filename => "test_data.txt",

    PORT MAP (

    PORT MAP (

      clk => clock,

      clk => clock,

      we  => we,

      we  => we,

      a1  => data_a,

      a1  => data_a,

      a2  => inst_a,

      a2  => inst_a,

      q2  => inst_o);

      q2  => inst_o);

  CTR1 : PROCESS (clock) IS

  CTR1 : PROCESS (clock) IS

  BEGIN  -- PROCESS CTR1

  BEGIN  -- PROCESS CTR1

    IF rising_edge(clock) THEN          -- rising clock edge

    IF rising_edge(clock) THEN          -- rising clock edge

        ctr_a <= 0;

        ctr_a <= 0;

      ELSE

      ELSE

        ctr_a <= ctr_a + 1;

        ctr_a <= ctr_a + 1;

      END IF;

      END IF;

    END IF;

    END IF;