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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.numeric_std.ALL;
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PACKAGE components IS
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COMPONENT data_reg
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GENERIC(
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w_data : NATURAL RANGE 1 TO 32 := 16;
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reset_value : NATURAL := 0);
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PORT (RST : IN STD_LOGIC;
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CLK : IN STD_LOGIC;
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ENA : IN STD_LOGIC;
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D : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Q : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT;
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COMPONENT queue IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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we : IN STD_LOGIC;
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sh : IN STD_LOGIC;
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clear : IN STD_LOGIC;
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC;
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d : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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q : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT queue;
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COMPONENT regf IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16;
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w_addr : NATURAL := 4);
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PORT (clk : IN STD_LOGIC;
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we : IN STD_LOGIC;
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a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);
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a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);
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d : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT;
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COMPONENT alu IS
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GENERIC(
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT(
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clk : IN STD_LOGIC;
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op : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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A : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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B : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT;
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COMPONENT incr
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GENERIC(
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT(
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A : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT;
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COMPONENT memory IS
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GENERIC(
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT(clk : IN STD_LOGIC;
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A1 : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
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B1 : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
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we : IN STD_LOGIC;
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D : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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A : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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B : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT;
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COMPONENT gpio_in
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GENERIC(
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w_data : NATURAL RANGE 1 TO 32 := 16;
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w_port : NATURAL RANGE 1 TO 32 := 16);
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PORT (rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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ena : IN STD_LOGIC;
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Q : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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port_in : IN STD_LOGIC_VECTOR(w_port - 1 DOWNTO 0));
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END COMPONENT;
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COMPONENT gpio_out
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GENERIC(
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w_data : NATURAL RANGE 1 TO 32 := 16;
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w_port : NATURAL RANGE 1 TO 32 := 16);
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PORT (rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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ena : IN STD_LOGIC;
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we : IN STD_LOGIC;
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D : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Q : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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port_out : OUT STD_LOGIC_VECTOR(w_port - 1 DOWNTO 0));
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END COMPONENT;
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COMPONENT decoder
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PORT (
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clk : IN STD_LOGIC;
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ena : IN STD_LOGIC;
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a1 : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
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gpio_1 : OUT STD_LOGIC;
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gpio_2 : OUT STD_LOGIC;
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gpio_3 : OUT STD_LOGIC;
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bus_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
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END COMPONENT;
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COMPONENT zerof
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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A : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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zero : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT clock_gen
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PORT (
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CLK_IN : IN STD_LOGIC;
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RESET : IN STD_LOGIC;
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CLK_VALID : OUT STD_LOGIC;
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CLK_OUT : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT sync_reset
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PORT (
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async_rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk_valid : IN STD_LOGIC;
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rst : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT control
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END COMPONENT;
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END components;
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