Subversion Repositories xucpu

LIBRARY ieee;

USE ieee.STD_LOGIC_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY data_reg_2 IS

  GENERIC (

    w_data      : NATURAL := 16;

    reset_value : NATURAL := 0);

  PORT (

    CLK : IN  STD_LOGIC;

    D   : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);

    Q   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));

END ENTITY data_reg_2;

ARCHITECTURE Behavioral OF data_reg_2 IS

BEGIN  -- ARCHITECTURE Behavioral

  -- purpose: Data register with synchronous reset

  -- type   : sequential

  -- inputs : CLK, RST, ENA, D

  -- outputs: Q

  DREG : PROCESS (CLK) IS

  BEGIN  -- PROCESS DREG

    IF rising_edge(CLK) THEN

          Q <= D;

    END IF;

  END PROCESS DREG;

END ARCHITECTURE Behavioral;