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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY incr IS
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GENERIC(
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT(
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A : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END ENTITY incr;
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ARCHITECTURE Behavioral OF incr IS
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BEGIN -- Behavioral
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Y <= STD_LOGIC_VECTOR(UNSIGNED(A) + to_unsigned(1, w_data));
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END Behavioral;
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