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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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PACKAGE mux_parts IS
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COMPONENT mux2to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT mux2to1;
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COMPONENT mux4to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT mux4to1;
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COMPONENT mux8to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT mux8to1;
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COMPONENT mux16to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S8 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S9 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S10 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S11 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S12 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S13 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S14 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S15 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END COMPONENT mux16to1;
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END mux_parts;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY mux2to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END mux2to1;
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ARCHITECTURE Behavioral OF mux2to1 IS
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BEGIN -- Behavioral
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WITH SEL SELECT
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Y <=
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S0 WHEN "0",
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S1 WHEN "1",
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S0 WHEN OTHERS;
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END Behavioral;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY mux4to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END mux4to1;
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ARCHITECTURE Behavioral OF mux4to1 IS
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BEGIN -- Behavioral
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WITH SEL SELECT
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Y <=
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S0 WHEN "00",
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S1 WHEN "01",
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S2 WHEN "10",
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S3 WHEN "11",
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S0 WHEN OTHERS;
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END Behavioral;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY mux8to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END mux8to1;
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ARCHITECTURE Behavioral OF mux8to1 IS
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BEGIN -- Behavioral
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WITH SEL SELECT
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Y <=
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S0 WHEN "000",
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S1 WHEN "001",
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S2 WHEN "010",
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S3 WHEN "011",
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S4 WHEN "100",
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S5 WHEN "101",
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S6 WHEN "110",
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S7 WHEN "111",
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S0 WHEN OTHERS;
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END Behavioral;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY mux16to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S8 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S9 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S10 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S11 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S12 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S13 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S14 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S15 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END mux16to1;
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ARCHITECTURE Behavioral OF mux16to1 IS
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BEGIN -- Behavioral
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WITH SEL SELECT
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Y <=
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S0 WHEN "0000",
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S1 WHEN "0001",
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S2 WHEN "0010",
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S3 WHEN "0011",
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S4 WHEN "0100",
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S5 WHEN "0101",
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S6 WHEN "0110",
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S7 WHEN "0111",
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S8 WHEN "1000",
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S9 WHEN "1001",
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S10 WHEN "1010",
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S11 WHEN "1011",
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S12 WHEN "1100",
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S13 WHEN "1101",
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S14 WHEN "1110",
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S15 WHEN "1111",
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S0 WHEN OTHERS;
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END Behavioral;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE work.mux_parts.ALL;
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ENTITY mux32to1 IS
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GENERIC (
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT (
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SEL : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S8 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S9 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S10 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S11 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S12 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S13 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S14 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S15 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S16 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S17 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S18 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S19 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S20 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S21 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S22 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S23 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S24 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S25 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S26 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S27 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S28 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S29 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S30 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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S31 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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END mux32to1;
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ARCHITECTURE Behavioral OF mux32to1 IS
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SIGNAL M1_Y : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL M2_Y : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL sub_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL out_sel : STD_LOGIC_VECTOR(0 DOWNTO 0);
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BEGIN -- Behavioral
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sub_sel <= SEL(3 DOWNTO 0);
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out_sel <= SEL(4 DOWNTO 4);
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M1 : mux16to1
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GENERIC MAP (
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w_data => w_data)
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PORT MAP (
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SEL => sub_sel,
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S0 => S0,
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S1 => S1,
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S2 => S2,
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S3 => S3,
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S4 => S4,
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S5 => S5,
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S6 => S6,
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S7 => S7,
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S8 => S8,
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S9 => S9,
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S10 => S10,
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S11 => S11,
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S12 => S12,
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S13 => S13,
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S14 => S14,
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S15 => S15,
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Y => M1_Y);
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M2 : mux16to1
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GENERIC MAP (
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w_data => w_data)
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PORT MAP (
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SEL => sub_sel,
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S0 => S16,
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S1 => S17,
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S2 => S18,
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S3 => S19,
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S4 => S20,
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S5 => S21,
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S6 => S22,
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S7 => S23,
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S8 => S24,
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S9 => S25,
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S10 => S26,
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S11 => S27,
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S12 => S28,
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S13 => S29,
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S14 => S30,
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S15 => S31,
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Y => M2_Y);
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M3 : mux2to1
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GENERIC MAP (
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w_data => w_data)
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PORT MAP (
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SEL => out_sel,
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S0 => M1_Y,
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S1 => M2_Y,
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Y => Y);
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END Behavioral;
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No newline at end of file
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No newline at end of file
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