URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [system/] [S2.vhdl] - Diff between revs 31 and 33

Rev 31	Rev 33
Line 86...	Line 86...
`I_RD => RD,`	`I_RD => RD,`
`I_WR => WR,`	`I_WR => WR,`
`-- CPU specific connections`	`-- CPU specific connections`
`I_CPU_IF => CPU_IF,`	`I_CPU_IF => CPU_IF,`
`I_CPU_INSTR_ADDR => CPU_INSTR_ADDR,`	`I_CPU_INSTR_ADDR => CPU_INSTR_ADDR,`
`I_CPU_INSTRUCTION => CPU_INSTRUCTION);`	`O_CPU_INSTRUCTION => CPU_INSTRUCTION);`

`DCC1 : S2DCC`	`DCC1 : S2DCC`
`PORT MAP (`	`PORT MAP (`
`-- Main component connections`	`-- Main component connections`
`CLK => CLK,`	`CLK => CLK,`
Line 108...	Line 108...
`I_RD => RD,`	`I_RD => RD,`
`I_WR => WR,`	`I_WR => WR,`
`-- CPU specific connections`	`-- CPU specific connections`
`I_CPU_RD => CPU_RD,`	`I_CPU_RD => CPU_RD,`
`I_CPU_WR => CPU_WR,`	`I_CPU_WR => CPU_WR,`
`I_CPU_DATA_ADDR => CPU_DATA_ADDRESS,`	`I_CPU_DATA_ADDR => CPU_DATA_ADDR,`
`I_CPU_DATA => CPU_DATA_OUT,`	`I_CPU_DATA => CPU_DATA_OUT,`
`O_CPU_DATA => CPU_DATA_IN);`	`O_CPU_DATA => CPU_DATA_IN);`

`CPU1 : S2CPU`	`CPU1 : S2CPU`
`PORT MAP (`	`PORT MAP (`
Line 124...	Line 124...
`O_INSTR_ADDR => CPU_INSTR_ADDR,`	`O_INSTR_ADDR => CPU_INSTR_ADDR,`
`I_INSTRUCTION => CPU_INSTRUCTION,`	`I_INSTRUCTION => CPU_INSTRUCTION,`
`-- Data cache connections`	`-- Data cache connections`
`O_RD => CPU_RD,`	`O_RD => CPU_RD,`
`O_WR => CPU_WR,`	`O_WR => CPU_WR,`
`O_DATA_ADDR => CPU_DATA_ADDRESS,`	`O_DATA_ADDR => CPU_DATA_ADDR,`
`O_DATA => CPU_DATA_OUT,`	`O_DATA => CPU_DATA_OUT,`
`I_DATA => CPU_DATA_IN);`	`I_DATA => CPU_DATA_IN);`

`MEM1 : S2MEM`	`MEM1 : S2MEM`
`PORT MAP (`	`PORT MAP (`