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[/] [xucpu/] [trunk/] [src/] [system/] [sync_reset.vhdl] - Diff between revs 2 and 6
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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY sync_reset IS
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PORT (
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async_rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk_valid : IN STD_LOGIC;
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rst : OUT STD_LOGIC);
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END ENTITY sync_reset;
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ARCHITECTURE Behavioral OF sync_reset IS
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SIGNAL count : INTEGER RANGE 0 TO 3 := 0;
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BEGIN -- Behavioral
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-- purpose: Turn asynchronous reset into synchronous reset
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-- type : sequential
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-- inputs : clk, async_rst, clk_valid
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-- outputs: rst
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reset : PROCESS (clk)
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BEGIN -- PROCESS reset
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IF rising_edge(clk) THEN
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IF clk_valid = '1' THEN
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IF count < 3 THEN
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count <= count + 1;
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ELSE
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count <= 3;
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END IF;
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ELSE
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count <= 0;
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END IF;
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END IF;
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END PROCESS reset;
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rst <= '1' WHEN count < 3 ELSE '0';
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END Behavioral;
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