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[/] [xucpu/] [trunk/] [src/] [system/] [system.vhdl] - Diff between revs 8 and 10
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| Rev 8 |
Rev 10 |
| Line 105... |
Line 105... |
SIGNAL ZERO : STD_LOGIC;
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SIGNAL ZERO : STD_LOGIC;
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SIGNAL INT : STD_LOGIC;
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SIGNAL INT : STD_LOGIC;
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BEGIN
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BEGIN
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-- Clock generator with selectable speed and reset
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-- Clock generator with selectable speed and reset
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CLOCK1 : clock_gen
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--CLOCK1 : clock_gen
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PORT MAP (
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-- PORT MAP (
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CLK_IN => CLOCK,
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-- CLK_IN => CLOCK,
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RESET => RESET,
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-- RESET => RESET,
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CLK_VALID => CLK_VAL,
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-- CLK_VALID => CLK_VAL,
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CLK_OUT => CLK);
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-- CLK_OUT => CLK);
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-- Synchronous reset
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-- Synchronous reset
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RST1 : sync_reset
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--RST1 : sync_reset
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PORT MAP (
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-- PORT MAP (
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ASYNC_RST => RESET,
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-- ASYNC_RST => RESET,
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CLK => CLK,
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-- CLK => CLK,
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CLK_VALID => CLK_VAL,
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-- CLK_VALID => CLK_VAL,
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RST => RST);
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-- RST => RST);
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CLK <= CLOCK;
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RST <= RESET;
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PC_TO_REG <= '0' & PC_OUT;
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PC_TO_REG <= '0' & PC_OUT;
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-- Input multiplexer to register file
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-- Input multiplexer to register file
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REG_MUX : mux8to1
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REG_MUX : mux8to1
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