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[/] [xucpu/] [trunk/] [src/] [system/] [system.vhdl] - Diff between revs 8 and 10

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Rev 8 Rev 10
Line 105... Line 105...
  SIGNAL ZERO   : STD_LOGIC;
  SIGNAL ZERO   : STD_LOGIC;
  SIGNAL INT    : STD_LOGIC;
  SIGNAL INT    : STD_LOGIC;
 
 
BEGIN
BEGIN
 
 
 
 
  -- Clock generator with selectable speed and reset
  -- Clock generator with selectable speed and reset
  CLOCK1 : clock_gen
  --CLOCK1 : clock_gen
    PORT MAP (
  --  PORT MAP (
      CLK_IN    => CLOCK,
  --    CLK_IN    => CLOCK,
      RESET     => RESET,
  --    RESET     => RESET,
      CLK_VALID => CLK_VAL,
  --    CLK_VALID => CLK_VAL,
      CLK_OUT   => CLK);
  --    CLK_OUT   => CLK);
 
 
  -- Synchronous reset
  -- Synchronous reset
  RST1 : sync_reset
  --RST1 : sync_reset
    PORT MAP (
  --  PORT MAP (
      ASYNC_RST => RESET,
  --    ASYNC_RST => RESET,
      CLK       => CLK,
  --    CLK       => CLK,
      CLK_VALID => CLK_VAL,
  --    CLK_VALID => CLK_VAL,
      RST       => RST);
  --    RST       => RST);
 
 
 
  CLK <= CLOCK;
 
  RST <= RESET;
 
 
  PC_TO_REG <= '0' & PC_OUT;
  PC_TO_REG <= '0' & PC_OUT;
 
 
  -- Input multiplexer to register file
  -- Input multiplexer to register file
  REG_MUX : mux8to1
  REG_MUX : mux8to1

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