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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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ARCHITECTURE Mealy OF uctrl IS
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TYPE uCtrl_state IS (
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S_RST,
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S_DECODE,
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S_FETCH,
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S_UOP_P1,
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S_UOP_P2,
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S_BOP_P1,
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S_BOP_P2,
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S_LD_RV,
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S_LD_RV_2,
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S_LD_RR,
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S_LD_RR_2,
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S_LD_RM,
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S_LD_RM_2,
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S_LD_MR,
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S_LD_MR_2,
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S_GO_ADR,
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S_GO_ADR_2,
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S_GO_REG,
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S_GO_REG_2,
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S_JZ_P0,
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S_JZ_P1,
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S_JZ_P2,
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S_JNZ_P0,
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S_JNZ_P1,
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S_JNZ_P2,
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S_HALT,
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S_RETI,
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S_RETI_2,
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S_ILL
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);
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SIGNAL NEXT_STATE : uCtrl_state;
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SIGNAL CURR_STATE : uCtrl_state;
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SIGNAL LD_INSTR : STD_LOGIC;
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SIGNAL DECODING : STD_LOGIC;
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SIGNAL OPERATION : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL REG_ADDR_A : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL REG_ADDR_B : STD_LOGIC_VECTOR(3 DOWNTO 0);
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BEGIN -- ARCHITECTURE Mealy
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-- purpose: Next state functionality
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-- type : combinational
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-- inputs : IR_IN,ZERO,INT,RST,CURR_STATE
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-- outputs:
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NEXT_ST1 : PROCESS (CURR_STATE, IR_IN, INT, RST, ZERO)
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VARIABLE I_ADDR : uCtrl_state;
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BEGIN -- PROCESS uCTRL
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IF RST = '1' THEN
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NEXT_STATE <= S_RST;
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ELSE
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CASE IR_IN(15 DOWNTO 12) IS
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WHEN "0000" => I_ADDR := S_HALT;
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WHEN "0001" => I_ADDR := S_GO_ADR;
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WHEN "0010" => I_ADDR := S_GO_REG;
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WHEN "0011" => I_ADDR := S_LD_RV;
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WHEN "0100" => I_ADDR := S_LD_RR;
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WHEN "0101" => I_ADDR := S_LD_RM;
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WHEN "0110" => I_ADDR := S_LD_MR;
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WHEN "0111" => I_ADDR := S_BOP_P1;
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WHEN "1000" => I_ADDR := S_UOP_P1;
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WHEN "1001" => I_ADDR := S_JZ_P0;
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WHEN "1010" => I_ADDR := S_JNZ_P0;
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WHEN "1011" => I_ADDR := S_RETI;
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WHEN "1100" => I_ADDR := S_ILL;
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WHEN "1101" => I_ADDR := S_ILL;
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WHEN "1110" => I_ADDR := S_ILL;
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WHEN "1111" => I_ADDR := S_ILL;
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WHEN OTHERS => I_ADDR := S_ILL;
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END CASE;
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CASE CURR_STATE IS
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WHEN S_RST =>
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NEXT_STATE <= S_FETCH;
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WHEN S_FETCH =>
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NEXT_STATE <= S_DECODE;
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WHEN S_DECODE =>
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NEXT_STATE <= I_ADDR;
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WHEN S_UOP_P1 =>
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NEXT_STATE <= S_UOP_P2;
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WHEN S_UOP_P2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_BOP_P1 =>
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NEXT_STATE <= S_BOP_P2;
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WHEN S_BOP_P2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_LD_RV =>
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NEXT_STATE <= S_LD_RV_2;
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WHEN S_LD_RV_2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_LD_RR =>
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NEXT_STATE <= S_LD_RR_2;
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WHEN S_LD_RR_2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_LD_RM =>
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NEXT_STATE <= S_LD_RM_2;
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WHEN S_LD_RM_2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_LD_MR =>
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NEXT_STATE <= S_LD_MR_2;
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WHEN S_LD_MR_2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_GO_ADR =>
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NEXT_STATE <= S_GO_ADR_2;
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WHEN S_GO_ADR_2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_GO_REG =>
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NEXT_STATE <= S_GO_REG_2;
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WHEN S_JZ_P0 =>
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NEXT_STATE <= S_JZ_P1;
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WHEN S_JZ_P1 =>
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IF ZERO = '1' THEN
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NEXT_STATE <= S_FETCH;
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ELSE
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NEXT_STATE <= S_JZ_P2;
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END IF;
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WHEN S_JZ_P2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_JNZ_P0 =>
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NEXT_STATE <= S_JNZ_P1;
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WHEN S_JNZ_P1 =>
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IF ZERO = '1' THEN
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NEXT_STATE <= S_FETCH;
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ELSE
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NEXT_STATE <= S_JZ_P2;
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END IF;
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WHEN S_JNZ_P2 =>
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NEXT_STATE <= I_ADDR;
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WHEN S_HALT =>
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NEXT_STATE <= S_HALT;
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WHEN S_RETI =>
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NEXT_STATE <= S_RETI_2;
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WHEN S_RETI_2 =>
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NEXT_STATE <= S_DECODE;
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WHEN S_ILL =>
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NEXT_STATE <= S_ILL;
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WHEN OTHERS =>
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NEXT_STATE <= S_DECODE;
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END CASE;
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END IF;
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END PROCESS NEXT_ST1;
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-- State register logic
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STATE_REG1 : PROCESS (CLK, RST)
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BEGIN
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IF rising_edge(CLK) THEN
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IF RST = '1' THEN
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CURR_STATE <= S_RST;
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ELSE
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CURR_STATE <= NEXT_STATE;
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END IF;
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END IF;
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END PROCESS STATE_REG1;
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-- Instruction values
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INSTR_REG1 : PROCESS (CLK, RST)
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BEGIN
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IF rising_edge(CLK) THEN
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IF RST = '1' THEN
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OPERATION <= "0000";
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REG_ADDR_A <= "0000";
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REG_ADDR_B <= "0000";
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ELSE
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IF LD_INSTR = '1' THEN
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OPERATION <= IR_IN(11 DOWNTO 8);
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REG_ADDR_A <= IR_IN(7 DOWNTO 4);
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REG_ADDR_B <= IR_IN(3 DOWNTO 0);
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END IF;
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END IF;
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END IF;
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END PROCESS;
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ALU_OP <= OPERATION;
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RFA_A <= REG_ADDR_A;
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RFA_B <= REG_ADDR_B;
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-- Mealy output function logic
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OUT1 : PROCESS (CURR_STATE, RST, INT, IR_IN, DECODING, ZERO)
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BEGIN
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-- Make sure that all control signals are initialised
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PC_SRC <= "011"; -- Default to PC output
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LD_PC <= '0';
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LD_IR <= '0';
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LD_DP <= '0';
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REG_SRC <= "101";
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REG_WR <= '0';
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LD_REG_A <= '0';
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LD_REG_B <= '0';
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LD_MAR <= '0';
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LD_MDR <= '0';
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MEM_WR <= '0';
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LD_INSTR <= '0';
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DECODING <= '0';
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CASE CURR_STATE IS
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WHEN S_RST =>
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IF RST = '0' THEN
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PC_SRC <= "100";
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LD_PC <= '1';
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LD_IR <= '0';
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END IF;
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WHEN S_FETCH =>
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '0';
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WHEN S_DECODE =>
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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WHEN S_UOP_P1 =>
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LD_REG_A <= '1';
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WHEN S_UOP_P2 =>
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REG_SRC <= "000";
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REG_WR <= '1';
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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WHEN S_BOP_P1 =>
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LD_REG_A <= '1';
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LD_REG_B <= '1';
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WHEN S_BOP_P2 =>
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REG_SRC <= "000";
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REG_WR <= '1';
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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WHEN S_LD_RR =>
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LD_REG_B <= '1';
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WHEN S_LD_RR_2 =>
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REG_SRC <= "000";
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REG_WR <= '1';
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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WHEN S_LD_RV =>
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '0';
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WHEN S_LD_RV_2 =>
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REG_SRC <= "010";
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REG_WR <= '1';
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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-- Write data from reg A to address reg B
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WHEN S_LD_MR =>
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LD_MAR <= '1';
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LD_MDR <= '1';
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WHEN S_LD_MR_2 =>
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MEM_WR <= '1';
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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WHEN S_LD_RM =>
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LD_MAR <= '1';
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WHEN S_LD_RM_2 =>
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REG_SRC <= "001";
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REG_WR <= '1';
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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WHEN S_JZ_P0 =>
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WHEN S_JNZ_P0 =>
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NULL;
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WHEN S_JZ_P1 =>
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IF ZERO = '1' THEN
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PC_SRC <= "010";
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ELSE
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PC_SRC <= "001";
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END IF;
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '0';
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WHEN S_JZ_P2 =>
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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WHEN S_JNZ_P1 =>
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IF ZERO = '0' THEN
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PC_SRC <= "010";
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ELSE
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PC_SRC <= "001";
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END IF;
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '0';
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WHEN S_JNZ_P2 =>
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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LD_INSTR <= '1';
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DECODING <= '1';
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WHEN S_HALT =>
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NULL;
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WHEN OTHERS =>
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PC_SRC <= "001";
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LD_PC <= '1';
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LD_IR <= '1';
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LD_DP <= '1';
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END CASE;
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CASE IR_IN(15 DOWNTO 12) IS
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WHEN "0001" =>
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IF DECODING = '1' THEN
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PC_SRC <= "111";
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LD_PC <= '1';
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END IF;
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WHEN "0011" =>
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WHEN "1001" =>
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WHEN "1010" =>
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IF DECODING = '1' THEN
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LD_IR <= '0';
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END IF;
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WHEN OTHERS =>
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NULL;
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END CASE;
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END PROCESS OUT1;
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END ARCHITECTURE Mealy;
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