Line 16... |
Line 16... |
-- It should be possible to generate this file based upon a
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-- It should be possible to generate this file based upon a
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-- description of the different devices.
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-- description of the different devices.
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ARCHITECTURE Structural OF board IS
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ARCHITECTURE Structural OF board IS
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-- System constants
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CONSTANT nr_of_masters : INTEGER := 2;
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CONSTANT nr_of_devices : INTEGER := 5;
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CONSTANT addr_width : INTEGER := 15;
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CONSTANT data_width : INTEGER := 16;
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-- Definition of bus signals
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-- Definition of bus signals
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SIGNAL data_bus : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL data_bus : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL address_bus : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL address_bus : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL bus_read : STD_LOGIC;
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SIGNAL bus_read : STD_LOGIC;
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SIGNAL bus_write : STD_LOGIC;
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SIGNAL bus_write : STD_LOGIC;
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SIGNAL bus_wait : STD_LOGIC;
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SIGNAL bus_wait : STD_LOGIC;
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SIGNAL bus_ack : STD_LOGIC;
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SIGNAL bus_ack : STD_LOGIC;
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-- Interconnection signals
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TYPE data_bus_array IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
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SIGNAL device_data_out : data_bus_array(0 TO nr_of_devices - 1);
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TYPE address_bus_array IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
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SIGNAL device_address_out : address_bus_array(0 TO nr_of_masters - 1);
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-- Board level components
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-- Clock buffer
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SIGNAL clk : STD_LOGIC := '0';
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-- From asynchronous reset to synchronous reset
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SIGNAL rst : STD_LOGIC := '0';
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-- Definition of components related to the bus
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-- Definition of components related to the bus
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COMPONENT data_mux IS
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COMPONENT data_mux IS
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PORT (
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PORT (
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data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0));
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data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0));
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Line 45... |
Line 67... |
END COMPONENT address_decoder;
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END COMPONENT address_decoder;
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COMPONENT bus_arbiter IS
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COMPONENT bus_arbiter IS
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END COMPONENT bus_arbiter;
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END COMPONENT bus_arbiter;
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-- Definition of components attached to the bus
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-- Definition of master devices attached to the bus
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COMPONENT icache IS
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PORT (
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
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addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
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data_rd : OUT STD_LOGIC;
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bus_wait : IN STD_LOGIC);
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END COMPONENT icache;
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COMPONENT dcache IS
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PORT (
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
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data_out : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
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addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
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data_rd : OUT STD_LOGIC;
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data_wr : OUT STD_LOGIC;
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bus_wait : IN STD_LOGIC);
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END COMPONENT dcache;
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-- Definition of io devices attached to the bus
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COMPONENT led_out IS
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PORT (
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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addr_in : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
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port_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
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END COMPONENT led_out;
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COMPONENT button_in IS
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PORT (
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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addr_in : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
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port_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
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END COMPONENT button_in;
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COMPONENT switch_in IS
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PORT (
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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addr_in : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
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port_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
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END COMPONENT switch_in;
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BEGIN -- ARCHITECTURE Structural
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BEGIN -- ARCHITECTURE Structural
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-- Mapping of bus related components
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-- Mapping of bus related components
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Line 60... |
Line 131... |
-- Instruction cache
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-- Instruction cache
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-- Data cache
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-- Data cache
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-- LED output device
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-- LED output device
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led_out_1 : led_out
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PORT MAP (
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clk => clk,
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rst => rst,
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data_in => data_bus(7 DOWNTO 0),
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addr_in => address_bus,
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port_out => led);
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-- Push button input device
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-- Push button input device
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button_in_1 : button_in
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PORT MAP (
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clk => clk,
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rst => rst,
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data_out => device_data_out(0)(7 DOWNTO 0),
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addr_in => address_bus,
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port_in => button);
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-- Slide switch input device
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-- Slide switch input device
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switch_in_1 : switch_in
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PORT MAP (
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clk => clk,
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rst => rst,
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data_out => device_data_out(1)(7 DOWNTO 0),
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addr_in => address_bus,
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port_in => switch);
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-- Serial communication device
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-- Serial communication device
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-- MAC device
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-- MAC device
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