| Line 65... |
Line 65... |
PORT (
|
PORT (
|
address_in : IN STD_LOGIC_VECTOR(14 DOWNTO 0));
|
address_in : IN STD_LOGIC_VECTOR(14 DOWNTO 0));
|
END COMPONENT address_decoder;
|
END COMPONENT address_decoder;
|
|
|
COMPONENT bus_arbiter IS
|
COMPONENT bus_arbiter IS
|
|
PORT (
|
|
clk : IN STD_LOGIC;
|
|
rst : IN STD_LOGIC;
|
|
rd_rq : IN STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
|
|
wr_rq : IN STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
|
|
master_ack : OUT STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0));
|
END COMPONENT bus_arbiter;
|
END COMPONENT bus_arbiter;
|
|
|
|
SIGNAL rd_rq : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
|
|
SIGNAL wr_rq : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
|
|
SIGNAL master_ack : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
|
|
|
-- Definition of master devices attached to the bus
|
-- Definition of master devices attached to the bus
|
COMPONENT icache IS
|
COMPONENT icache IS
|
PORT (
|
PORT (
|
clk : IN STD_LOGIC;
|
clk : IN STD_LOGIC;
|
rst : IN STD_LOGIC;
|
rst : IN STD_LOGIC;
|
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
|
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
|
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
|
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
|
data_rd : OUT STD_LOGIC;
|
data_rd : OUT STD_LOGIC;
|
bus_wait : IN STD_LOGIC);
|
bus_wait : IN STD_LOGIC;
|
|
master_ack : IN STD_LOGIC);
|
END COMPONENT icache;
|
END COMPONENT icache;
|
|
|
COMPONENT dcache IS
|
COMPONENT dcache IS
|
PORT (
|
PORT (
|
clk : IN STD_LOGIC;
|
clk : IN STD_LOGIC;
|
| Line 87... |
Line 98... |
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
|
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
|
data_out : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
|
data_out : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
|
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
|
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
|
data_rd : OUT STD_LOGIC;
|
data_rd : OUT STD_LOGIC;
|
data_wr : OUT STD_LOGIC;
|
data_wr : OUT STD_LOGIC;
|
bus_wait : IN STD_LOGIC);
|
bus_wait : IN STD_LOGIC;
|
|
master_ack : IN STD_LOGIC);
|
END COMPONENT dcache;
|
END COMPONENT dcache;
|
|
|
-- Definition of io devices attached to the bus
|
-- Definition of io devices attached to the bus
|
COMPONENT led_out IS
|
COMPONENT led_out IS
|
PORT (
|
PORT (
|
| Line 121... |
Line 133... |
END COMPONENT switch_in;
|
END COMPONENT switch_in;
|
|
|
BEGIN -- ARCHITECTURE Structural
|
BEGIN -- ARCHITECTURE Structural
|
|
|
-- Mapping of bus related components
|
-- Mapping of bus related components
|
|
bus_arbiter_1 : bus_arbiter
|
|
PORT MAP (
|
|
clk => clk,
|
|
rst => rst,
|
|
rd_rq => rd_rq,
|
|
wr_rq => wr_rq,
|
|
master_ack => master_ack);
|
|
|
-- Mapping of system devices
|
-- Mapping of system devices
|
|
|
-- Main memory
|
-- Main memory
|
|
|
-- Instruction cache
|
-- Instruction cache
|
|
icache_1 : icache
|
|
PORT MAP (
|
|
clk => clk,
|
|
rst => rst,
|
|
data_in => data_bus,
|
|
addr_out => device_address_out(0),
|
|
data_rd => rd_rq(0),
|
|
bus_wait => bus_wait,
|
|
master_ack => master_ack(0));
|
|
|
-- Data cache
|
-- Data cache
|
|
dcache_1 : dcache
|
|
PORT MAP (
|
|
clk => clk,
|
|
rst => rst,
|
|
data_in => data_bus,
|
|
data_out => device_data_out(1),
|
|
addr_out => device_address_out(1),
|
|
data_rd => rd_rq(1),
|
|
data_wr => wr_rq(1),
|
|
bus_wait => bus_wait,
|
|
master_ack => master_ack(0));
|
|
|
-- LED output device
|
-- LED output device
|
led_out_1 : led_out
|
led_out_1 : led_out
|
PORT MAP (
|
PORT MAP (
|
clk => clk,
|
clk => clk,
|
| Line 144... |
Line 183... |
-- Push button input device
|
-- Push button input device
|
button_in_1 : button_in
|
button_in_1 : button_in
|
PORT MAP (
|
PORT MAP (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
data_out => device_data_out(0)(7 DOWNTO 0),
|
data_out => device_data_out(3)(7 DOWNTO 0),
|
addr_in => address_bus,
|
addr_in => address_bus,
|
port_in => button);
|
port_in => button);
|
|
|
-- Slide switch input device
|
-- Slide switch input device
|
switch_in_1 : switch_in
|
switch_in_1 : switch_in
|
PORT MAP (
|
PORT MAP (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
data_out => device_data_out(1)(7 DOWNTO 0),
|
data_out => device_data_out(4)(7 DOWNTO 0),
|
addr_in => address_bus,
|
addr_in => address_bus,
|
port_in => switch);
|
port_in => switch);
|
|
|
-- Serial communication device
|
-- Serial communication device
|
|
|
