URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [simulation.wcfg] - Diff between revs 12 and 41
Show entire file |
Details |
Blame |
View Log
Rev 12 |
Rev 41 |
?rev1line? |
?rev2line? |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clock
|
|
clock
|
|
|
|
|
|
label
|
|
clock
|
|
clock
|
|
uc_clock
|
|
|
|
|
|
label
|
|
clock
|
|
clock
|
|
dp_clock
|
|
|
|
|
|
clka
|
|
clka
|
|
|
|
|
|
clka
|
|
clka
|
|
|
|
|
|
clka
|
|
clka
|
|
|
|
|
|
clka
|
|
clka
|
|
|
|
|
|
label
|
|
clka
|
|
clka
|
|
mem_clka
|
|
|
|
|
|
reset
|
|
reset
|
|
|
|
|
|
clk_valid
|
|
clk_valid
|
|
|
|
|
|
switch_in[7:0]
|
|
switch_in[7:0]
|
|
|
|
|
|
pushb_in[4:0]
|
|
pushb_in[4:0]
|
|
|
|
|
|
led_out[7:0]
|
|
led_out[7:0]
|
|
|
|
|
|
pc[14:0]
|
|
pc[14:0]
|
|
|
|
|
|
reg_a[3:0]
|
|
reg_a[3:0]
|
|
|
|
|
|
reg_b[3:0]
|
|
reg_b[3:0]
|
|
|
|
|
|
op_sel[3:0]
|
|
op_sel[3:0]
|
|
|
|
|
|
data_in[15:0]
|
|
data_in[15:0]
|
|
|
|
|
|
memw
|
|
memw
|
|
|
|
|
|
memr
|
|
memr
|
|
|
|
|
|
[3]
|
|
addra[3]
|
|
|
|
|
|
doa[31:0]
|
|
doa[31:0]
|
|
|
|
|
|
wea[3:0]
|
|
wea[3:0]
|
|
|
|
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.