URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [startup_sim_pr.wcfg] - Diff between revs 12 and 41
Show entire file |
Details |
Blame |
View Log
| Rev 12 |
Rev 41 |
?rev1line? |
?rev2line? |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clock
|
|
clock
|
|
|
|
|
|
reset
|
|
reset
|
|
|
|
|
|
clk_out
|
|
clk_out
|
|
|
|
|
|
rst
|
|
rst
|
|
|
|
|
|
y[14:0]
|
|
y[14:0]
|
|
|
|
|
|
ld_pc
|
|
ld_pc
|
|
|
|
|
|
ld_ir
|
|
ld_ir
|
|
|
|
|
|
ld_dp
|
|
ld_dp
|
|
|
|
|
|
q[14:0]
|
|
q[14:0]
|
|
|
|
|
|
a2[9:0]
|
|
a2[9:0]
|
|
|
|
|
|
q2[15:0]
|
|
q2[15:0]
|
|
|
|
|
|
q[15:0]
|
|
q[15:0]
|
|
|
|
|
|
q[15:0]
|
|
q[15:0]
|
|
|
|
|
|
operation[3:0]
|
|
operation[3:0]
|
|
|
|
|
|
reg_addr_a[3:0]
|
|
reg_addr_a[3:0]
|
|
|
|
|
|
reg_addr_b[3:0]
|
|
reg_addr_b[3:0]
|
|
|
|
|
|
reg_wr
|
|
reg_wr
|
|
|
|
|
|
reg_src[2:0]
|
|
reg_src[2:0]
|
|
|
|
|
|
d[15:0]
|
|
d[15:0]
|
|
|
|
|
|
q1[15:0]
|
|
q1[15:0]
|
|
|
|
|
|
label
|
|
q2[15:0]
|
|
q2[15:0]
|
|
q2[15:0]
|
|
|
|
|
|
zero
|
|
zero
|
|
|
|
|
|
Memory
|
|
label
|
|
128 128 255
|
|
230 230 230
|
|
|
|
|
|
mem_wr
|
|
mem_wr
|
|
|
|
|
|
data_address[14:0]
|
|
data_address[14:0]
|
|
|
|
|
|
databus_write[15:0]
|
|
databus_write[15:0]
|
|
|
|
|
|
led_out[7:0]
|
|
led_out[7:0]
|
|
|
|
|
|
gpio_1
|
|
gpio_1
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
