URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
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Rev 41 |
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/clock_gen - Behavioral |home|jurgen|Projects|xucpu|src|system|clock.vhdl
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/memory - Structural |home|jurgen|Projects|xucpu|src|components|BRAM|RAM.vhdl
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/mux32to1 - Behavioral |home|jurgen|Projects|xucpu|src|components|multiplexer|MUX.vhdl
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/summation - Behavioral |home|jurgen|Projects|xucpu|src|components|ALU|summation.vhdl
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/system - Structural |home|jurgen|Projects|xucpu|src|system|system_4k.vhdl
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/system - Structural |home|jurgen|Projects|xucpu|src|system|system_mem_32k.vhdl
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system - Structural (/home/jurgen/Projects/xucpu/src/system/system_4k.vhdl)
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000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000294000000020000000000000000000000000200000064ffffffff000000810000000300000002000002940000000100000003000000000000000100000003
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false
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system - Structural (/home/jurgen/Projects/xucpu/src/system/system_4k.vhdl)
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1
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Configure Target Device
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Design Utilities
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Implement Design/Map
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Implement Design/Place & Route/Back-annotate Pin Locations
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Implement Design/Place & Route/Generate IBIS Model
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Implement Design/Translate
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User Constraints
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Analyze Post-Place & Route Static Timing
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000000ff000000000000000100000001000000000000000000000000000000000000000000000001c8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001c80000000100000000
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false
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Analyze Post-Place & Route Static Timing
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1
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000000ff000000000000000100000000000000000100000000000000000000000000000000000003e1000000040101000100000000000000000000000064ffffffff0000008100000000000000040000021b0000000100000000000000d00000000100000000000000840000000100000000000000720000000100000000
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false
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/home/jurgen/Projects/xucpu/src/components/ALU/alu2.vhdl
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1
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work
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0
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0
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000000ff000000000000000100000000000000000100000000000000000000000000000000000001d8000000010001000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000
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false
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work
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000000ff0000000000000002000001490000012001000000060100000002
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Implementation
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