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# Copyright 2015, Jürgen Defurne
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#
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# This file is part of the Experimental Unstable CPU System.
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#
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# The Experimental Unstable CPU System Is free software: you can redistribute
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# it and/or modify it under the terms of the GNU Lesser General Public License
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# as published by the Free Software Foundation, either version 3 of the
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# License, or (at your option) any later version.
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#
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# The Experimental Unstable CPU System is distributed in the hope that it will
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# be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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# General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public License
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# along with Experimental Unstable CPU System. If not, see
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# http://www.gnu.org/licenses/lgpl.txt.
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FIND=find
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XARGS=xargs
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UNISIM=D:/cygwin64/usr/local/share
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SOURCE= ../src/file/arrayio.vhdl \
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../src/multiplexer/MUX.vhdl \
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../src/blockram/RAM.vhdl \
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../src/components.vhdl \
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../src/ALU/alu.vhdl \
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../src/ALU/logic.vhdl \
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../src/ALU/shift.vhdl \
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../src/ALU/summation.vhdl \
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../src/controllers.vhdl \
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../src/uctrl.vhdl \
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../src/system.vhdl \
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../src/gpio_in.vhdl \
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../src/gpio_out.vhdl \
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../src/incr.vhdl \
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../src/regf.vhdl \
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../src/sync_reset.vhdl \
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../src/zerof.vhdl \
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../src/decoder.vhdl \
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../src/system_sim.vhdl \
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../src/startup_sim.vhdl \
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../src/clock.vhdl \
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../Xilinx/ipcore_dir/clock_core_gen.vhd \
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../src/data_reg.vhdl
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unisim: unisim-obj93.cf
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ghdl -a --ieee=synopsys --work=unisim --workdir=tmp $(UNISIM)/unisims/*.vhd
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$(FIND) $(UNISIM)/unisims/primitive/*.vhd -print0 | $(XARGS) -0 -n 1 -t ghdl -a --ieee=synopsys --work=unisim --workdir=tmp -fexplicit
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unisim-obj93.cf:
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analyse:
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ghdl -a -P./. -P./tmp --ieee=synopsys --workdir=tmp $(SOURCE)
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build: unisim-obj93.cf analyse
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ghdl -e -g -P./. -P./tmp --warn-unused --ieee=synopsys --workdir=tmp startup_sim
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run: build
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ghdl -r -P. startup_sim --wave=startup_sim.ghw --stop-time=2us
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clean:
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-rm *.o
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-rm unisim*
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init: cp_init
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cp_init:
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cp uctrl-init.vhdl uctrl.vhdl
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main: cp_main
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cp_main:
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cp uctrl-main.vhdl uctrl.vhdl
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test: cp_test
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cp_test:
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cp test/$(INST).txt input_data.txt
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# vim:set noet tw=0 ts=8:
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