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[/] [xulalx25soc/] [trunk/] [bench/] [asm/] [memtest.s] - Diff between revs 15 and 35

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Line 1... Line 1...
////////////////////////////////////////////////////////////////////////////////
;///////////////////////////////////////////////////////////////////////////////
//
;/
// Filename:    memtest.S
;/ Filename:    memtest.S
//
;/
// Project:     XuLA2 board
;/ Project:     XuLA2 board
//
;/
// Purpose:     To test whether or not we can interface with the SDRAM on the
;/ Purpose:     To test whether or not we can interface with the SDRAM on the
//              XuLA2 board.
;/              XuLA2 board.
//
;/
//
;/
// Creator:     Dan Gisselquist, Ph.D.
;/ Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
;/              Gisselquist Technology, LLC
//
;/
////////////////////////////////////////////////////////////////////////////////
;///////////////////////////////////////////////////////////////////////////////
//
;/
// Copyright (C) 2015, Gisselquist Technology, LLC
;/ Copyright (C) 2015, Gisselquist Technology, LLC
//
;/
// This program is free software (firmware): you can redistribute it and/or
;/ This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
;/ modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
;/ by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
;/ your option) any later version.
//
;/
// This program is distributed in the hope that it will be useful, but WITHOUT
;/ This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
;/ ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
;/ FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
;/ for more details.
//
;/
// License:     GPL, v3, as defined and found on www.gnu.org,
;/ License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
;/              http://www.gnu.org/licenses/gpl.html
//
;/
//
;/
////////////////////////////////////////////////////////////////////////////////
;///////////////////////////////////////////////////////////////////////////////
//
;/
//
;/
#define LFSRFILL        0x000001
#define LFSRFILL        0x000001
// #define      LFSRTAPS        0x004597f
;/ #define      LFSRTAPS        0x004597f
#define LFSRTAPS        0x0408b85
#define LFSRTAPS        0x0408b85
#define SDRAMBASE       0x0800000
#define SDRAMBASE       0x0800000
// #define      SDRAMLEN        0x0800000
;/ #define      SDRAMLEN        0x0800000
#define SDRAMLEN        0x0800000
#define SDRAMLEN        0x0800000
#define RAMSCOPE        0x011c
#define RAMSCOPE        0x011c
#define ZIPSCOPE        0x011e
#define ZIPSCOPE        0x011e
master_entry:
        .section .start
        MOV     user_entry(PC),uPC
        .global _start
 
        .type   _start,@function
 
_start:
 
        LDI     user_entry,R0
 
        MOV     R0,uPC
        ; LDI   RAMSCOPE,R8
        ; LDI   RAMSCOPE,R8
        ; LDI   0x04000000,R9
        ; LDI   0x04000000,R9
        ; STO   R9,(R8)
        ; STO   R9,(R8)
        RTU
        RTU
        ; // Capture what just happened
        ; // Capture what just happened
        ; LDI   0x8c000000,R9
        ; LDI   0x8c000000,R9
        ; STO   R9,(R8)
        ; STO   R9,(R8)
        ; NOP
        ; NOP
        ; 
        ; 
        HALT
        HALT
 
        .section .text
user_entry:
user_entry:
// #define      CLEAR_MEMORY
;/ #define      CLEAR_MEMORY
#ifdef  CLEAR_MEMORY
#ifdef  CLEAR_MEMORY
clear_memory:
clear_memory:
        LDI     SDRAMBASE,R0
        LDI     SDRAMBASE,R0
        LDI     SDRAMLEN,R1
        LDI     SDRAMLEN,R1
        ADD     R0,R1
        ADD     R0,R1
Line 77... Line 81...
        LDI     SDRAMBASE,R0
        LDI     SDRAMBASE,R0
        LDI     SDRAMLEN,R1
        LDI     SDRAMLEN,R1
        MOV     R2,R7           ; Copy our initial fill
        MOV     R2,R7           ; Copy our initial fill
        CMP     0,R2
        CMP     0,R2
        HALT.Z
        HALT.Z
// #define      WAIT_FOR_WRITE_SCOPE
;/ #define      WAIT_FOR_WRITE_SCOPE
#ifdef  WAIT_FOR_WRITE_SCOPE
#ifdef  WAIT_FOR_WRITE_SCOPE
        LDI     RAMSCOPE,R8
        LDI     RAMSCOPE,R8
        LDI     0x01ffc,R9
        LDI     0x01ffc,R9
        STO     R9,(R8)                 ; Reset the SDRAM scope
        STO     R9,(R8)                 ; Reset the SDRAM scope
        NOP                             ; Give it a chance to reset
        NOP                             ; Give it a chance to reset
Line 114... Line 118...
        BGE     write_test_loop
        BGE     write_test_loop
 
 
read_test:
read_test:
        LDI     SDRAMBASE,R0
        LDI     SDRAMBASE,R0
        LDI     SDRAMLEN,R1
        LDI     SDRAMLEN,R1
// #define      WAIT_FOR_READ_SCOPE
;/ #define      WAIT_FOR_READ_SCOPE
#ifdef  WAIT_FOR_READ_SCOPE
#ifdef  WAIT_FOR_READ_SCOPE
        LDI     RAMSCOPE,R8
        LDI     RAMSCOPE,R8
        LDI     0x01ffc,R9
        LDI     0x01ffc,R9
        STO     R9,(R8)                 ; Reset the SDRAM scope
        STO     R9,(R8)                 ; Reset the SDRAM scope
        NOP                             ; Give it a chance to reset
        NOP                             ; Give it a chance to reset
Line 127... Line 131...
        NOP
        NOP
        LOD     (R8),R9
        LOD     (R8),R9
        TST     R10,R9
        TST     R10,R9
        BZ      not_ready
        BZ      not_ready
#endif
#endif
//
;/
//      RAM[49072] = 0x02b39ba ... not RAM[0].  What's going on here?
;/      RAM[49072] = 0x02b39ba ... not RAM[0].  What's going on here?
//
;/      
read_test_loop:
read_test_loop:
        LOD     (R0),R4
        LOD     (R0),R4
        LOD     1(R0),R5
        LOD     1(R0),R5
        LOD     2(R0),R6
        LOD     2(R0),R6
 
 
        LSR     1,R7
        LSR     1,R7
        XOR.C   R3,R7
        XOR.C   R3,R7
        CMP     R7,R4
        CMP     R7,R4
        TRAP.NZ 0
        TRAP.NZ 0
 
 
        LSR     1,R7
        LSR     1,R7
        XOR.C   R3,R7
        XOR.C   R3,R7
        CMP     R7,R5
        CMP     R7,R5
        TRAP.NZ 0
        TRAP.NZ 0
 
 
        LSR     1,R7
        LSR     1,R7
        XOR.C   R3,R7
        XOR.C   R3,R7
        CMP     R7,R6
        CMP     R7,R6
        TRAP.NZ 0
        TRAP.NZ 0
 
 
        ADD     3,R0
        ADD     3,R0
        SUB     3,R1
        SUB     3,R1
        CMP     3,R1
        CMP     3,R1
 
 
        BGE     read_test_loop
        BGE     read_test_loop
 
 
        ADD     1,R12
        ADD     1,R12
        BRA     write_test
        BRA     write_test
;
 
;
 
;
 
;       0x0408b85
 
;       0x060ce47
 
;       0x070eca6
 
;       0x0387653
 
;       0x05cb0ac
 
;       0x02e5856
 
;       0x0172c2b
 
;       0x04b1d90
 
;       0x0258ec8
 
;       0x012c764
 
;       0x00963b2
 
;       0x004b1d9
 
;       0x042d369
 
;       0x061e231
 
;       0x0707a9d
 
;       ...
 
;
 
;
 
 
 
 No newline at end of file
 No newline at end of file
 
;
 
;
 
;
 
;       0x0408b85
 
;       0x060ce47
 
;       0x070eca6
 
;       0x0387653
 
;       0x05cb0ac
 
;       0x02e5856
 
;       0x0172c2b
 
;       0x04b1d90
 
;       0x0258ec8
 
;       0x012c764
 
;       0x00963b2
 
;       0x004b1d9
 
;       0x042d369
 
;       0x061e231
 
;       0x0707a9d
 
;       ...
 
;
 
;
 
 
 No newline at end of file
 No newline at end of file

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