| Line 40... |
Line 40... |
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
#include <signal.h>
|
#include <signal.h>
|
#include <time.h>
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#include <time.h>
|
|
#include <ctype.h>
|
|
|
#include "verilated.h"
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#include "verilated.h"
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#include "Vbusmaster.h"
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#include "Vbusmaster.h"
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|
|
#include "testb.h"
|
#include "testb.h"
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// #include "twoc.h"
|
// #include "twoc.h"
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#include "pipecmdr.h"
|
#include "pipecmdr.h"
|
#include "qspiflashsim.h"
|
#include "qspiflashsim.h"
|
#include "sdramsim.h"
|
#include "sdramsim.h"
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#include "sdspisim.h"
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#include "sdspisim.h"
|
|
#include "uartsim.h"
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|
|
#include "port.h"
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#include "port.h"
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|
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// Add a reset line, since Vbusmaster doesn't have one
|
// Add a reset line, since Vbusmaster doesn't have one
|
class Vbusmasterr : public Vbusmaster {
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class Vbusmasterr : public Vbusmaster {
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| Line 70... |
Line 72... |
SDSPISIM m_sdcard;
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SDSPISIM m_sdcard;
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SDRAMSIM m_sdram;
|
SDRAMSIM m_sdram;
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unsigned m_last_led;
|
unsigned m_last_led;
|
time_t m_start_time;
|
time_t m_start_time;
|
bool m_last_writeout;
|
bool m_last_writeout;
|
|
UARTSIM m_uart;
|
|
|
BUSMASTER_TB(void) : PIPECMDR(FPGAPORT) {
|
BUSMASTER_TB(void) : PIPECMDR(FPGAPORT), m_uart(FPGAPORT+1) {
|
m_start_time = time(NULL);
|
m_start_time = time(NULL);
|
}
|
}
|
|
|
void reset(void) {
|
void reset(void) {
|
m_core->i_clk = 1;
|
m_core->i_clk = 1;
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| Line 122... |
Line 125... |
m_core->o_ram_cke, m_core->o_ram_cs_n,
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m_core->o_ram_cke, m_core->o_ram_cs_n,
|
m_core->o_ram_ras_n, m_core->o_ram_cas_n,
|
m_core->o_ram_ras_n, m_core->o_ram_cas_n,
|
m_core->o_ram_we_n, m_core->o_ram_bs,
|
m_core->o_ram_we_n, m_core->o_ram_bs,
|
m_core->o_ram_addr, m_core->o_ram_drive_data,
|
m_core->o_ram_addr, m_core->o_ram_drive_data,
|
m_core->o_ram_data);
|
m_core->o_ram_data);
|
|
|
|
m_core->i_rx_uart = m_uart(m_core->o_tx_uart,
|
|
m_core->v__DOT__serialport__DOT__r_setup);
|
PIPECMDR::tick();
|
PIPECMDR::tick();
|
|
|
bool writeout = false;
|
bool writeout = false;
|
/*
|
|
if (m_core->v__DOT__sdram__DOT__r_pending)
|
|
writeout = true;
|
|
else if (m_core->v__DOT__sdram__DOT__bank_active[0])
|
|
writeout = true;
|
|
else if (m_core->v__DOT__sdram__DOT__bank_active[1])
|
|
writeout = true;
|
|
else if (m_core->v__DOT__sdram__DOT__bank_active[2])
|
|
writeout = true;
|
|
else if (m_core->v__DOT__sdram__DOT__bank_active[3])
|
|
writeout = true;
|
|
*/
|
|
|
|
if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
|
|
writeout = true;
|
|
/*
|
|
if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
|
|
writeout = true;
|
|
if (m_core->v__DOT__genbus__DOT__exec_stb)
|
|
writeout = true;
|
|
*/
|
|
|
|
#define v__DOT__wb_addr v__DOT__dwb_addr
|
|
#define v__DOT__dwb_stall v__DOT__wb_stall
|
|
#define v__DOT__dwb_ack v__DOT__wb_ack
|
|
#define v__DOT__wb_cyc v__DOT__dwb_cyc
|
|
#define v__DOT__wb_stb v__DOT__dwb_stb
|
|
#define v__DOT__wb_we v__DOT__dwb_we
|
|
#define v__DOT__dwb_idata v__DOT__wb_idata
|
|
#define v__DOT__wb_data v__DOT__dwb_odata
|
|
|
|
if (!m_core->v__DOT__zippy__DOT__cmd_halt)
|
|
writeout = true;
|
|
|
|
if (!m_core->o_sd_cs_n)
|
|
writeout = true;
|
|
else if (!m_core->v__DOT__sdcard_cs_n)
|
|
writeout = true;
|
|
else if ((((m_core->v__DOT__wb_addr ^ 0x0120)&(~0x03))==0)
|
|
&&(m_core->v__DOT__wb_cyc))
|
|
writeout = true;
|
|
|
|
/*
|
|
writeout = (writeout)||(m_core->i_rx_stb)
|
|
||((m_core->o_tx_stb)&&(!m_core->i_tx_busy));
|
|
writeout = (writeout)||(m_core->v__DOT____Vcellinp__genbus____pinNumber9);
|
|
writeout = (writeout)||(m_core->v__DOT__wb_stb);
|
|
writeout = (writeout)||(m_core->v__DOT__wb_err);
|
|
*/
|
|
|
|
if ((writeout)||(m_last_writeout)) {
|
if ((writeout)||(m_last_writeout)) {
|
printf("%08lx:", m_tickcount);
|
printf("%08lx:", m_tickcount);
|
|
|
/*
|
|
printf("%d/%02x %d/%02x%s ",
|
|
m_core->i_rx_stb, m_core->i_rx_data,
|
|
m_core->o_tx_stb, m_core->o_tx_data,
|
|
m_core->i_tx_busy?"/BSY":" ");
|
|
*/
|
|
|
|
printf("(%d,%d->%d),(%c:%d,%d->%d)|%c[%08x/%08x]@%08x %c%c%c",
|
|
m_core->v__DOT__wbu_cyc,
|
|
m_core->v__DOT__dwb_cyc, // was zip_cyc
|
|
m_core->v__DOT__wb_cyc,
|
|
//
|
|
m_core->v__DOT__wbu_zip_arbiter__DOT__r_a_owner?'Z':'j',
|
|
m_core->v__DOT__wbu_stb,
|
|
// 0, // m_core->v__DOT__dwb_stb, // was zip_stb
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl,
|
|
m_core->v__DOT__wb_stb,
|
|
//
|
|
(m_core->v__DOT__wb_we)?'W':'R',
|
|
m_core->v__DOT__wb_data,
|
|
m_core->v__DOT__dwb_idata,
|
|
m_core->v__DOT__wb_addr,
|
|
(m_core->v__DOT__dwb_ack)?'A':
|
|
(m_core->v__DOT____Vcellinp__genbus____pinNumber9)?'a':' ',
|
|
(m_core->v__DOT__dwb_stall)?'S':
|
|
(m_core->v__DOT____Vcellinp__genbus____pinNumber10)?'s':' ',
|
|
(m_core->v__DOT__wb_err)?'E':'.');
|
|
|
|
printf(" RUNWB %d:%09lx %d@0x%08x %3x %3x %d %d/%d/%d %d:%09lx",
|
|
m_core->v__DOT__genbus__DOT__fifo_in_stb,
|
|
m_core->v__DOT__genbus__DOT__fifo_in_word,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
|
|
m_core->v__DOT__wbu_addr,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__w_eow,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__last_read_request,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__last_ack,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__zero_acks,
|
|
m_core->v__DOT__genbus__DOT__exec_stb,
|
|
m_core->v__DOT__genbus__DOT__exec_word);
|
|
|
|
printf(" WBU[%d,%3d,%3d]",
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed);
|
|
|
|
/*
|
|
printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c",
|
|
(m_core->v__DOT__sdram_sel)?'!':' ',
|
|
m_core->o_ram_cs_n, m_core->o_ram_ras_n,
|
|
m_core->o_ram_cas_n, m_core->o_ram_we_n,
|
|
m_core->o_ram_bs, m_core->o_ram_data,
|
|
(m_core->o_ram_drive_data)?'D':'-',
|
|
m_core->o_ram_addr,
|
|
(m_core->o_ram_addr>>10)&1,
|
|
m_core->i_ram_data,
|
|
(m_core->o_ram_drive_data)?'-':'V');
|
|
|
|
printf(" SD[%d,%d-%3x%d]",
|
|
m_core->v__DOT__sdram__DOT__r_state,
|
|
m_sdram.pwrup(),
|
|
m_core->v__DOT__sdram__DOT__refresh_clk,
|
|
m_core->v__DOT__sdram__DOT__need_refresh);
|
|
|
|
printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d",
|
|
m_core->v__DOT__sdram__DOT__bank_active[0],
|
|
m_core->v__DOT__sdram__DOT__bank_row[0],
|
|
m_core->v__DOT__sdram__DOT__bank_active[1],
|
|
m_core->v__DOT__sdram__DOT__bank_row[1],
|
|
m_core->v__DOT__sdram__DOT__bank_active[2],
|
|
m_core->v__DOT__sdram__DOT__bank_row[2],
|
|
m_core->v__DOT__sdram__DOT__bank_active[3],
|
|
m_core->v__DOT__sdram__DOT__bank_row[3],
|
|
m_core->v__DOT__sdram__DOT__clocks_til_idle,
|
|
m_core->v__DOT__sdram__DOT__r_barrell_ack);
|
|
|
|
printf(" %s%s%c[%08x@%06x]",
|
|
(m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ",
|
|
(m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ",
|
|
(m_core->v__DOT__sdram__DOT__r_we)?'W':'R',
|
|
(m_core->v__DOT__sdram__DOT__r_we)
|
|
?(m_core->v__DOT__sdram__DOT__r_data)
|
|
:(m_core->v__DOT__sdram_data),
|
|
(m_core->v__DOT__sdram__DOT__r_addr));
|
|
*/
|
|
|
|
/*
|
|
printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%2x %s%s %2d %2d",
|
|
// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-",
|
|
// (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-",
|
|
// (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-",
|
|
(m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_halted)?"Z":"-",
|
|
(m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_valid)?"V":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_gbl)?"G":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_lcl)?"L":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)?"D":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_ce)?"d":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_alu)?"A":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_ce)?"a":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_mem)?"M":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_ce)?"m":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__clear_pipeline)?"C":"-",
|
|
(m_core->v__DOT__zippy__DOT__cmd_addr),
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ibus_err_flag)?"IB":" ",
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ubus_err_flag)?"UB":" ",
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__rdaddr,
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__wraddr);
|
|
|
|
printf(" PC0x%08x/%08x/%08x-%08x %s0x%08x",
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_pc,
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__ipc,
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__upc,
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction,
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":" ",
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc
|
|
);
|
|
|
|
printf(" %s[%02x]=%08x(%08x)",
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_ce?"WR":"--",
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_id,
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_gpreg_vl,
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_spreg_vl);
|
|
*/
|
|
|
|
|
|
/*
|
|
printf(" SDSPI[%d,%d(%d),(%d)]",
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_busy,
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_state,
|
|
m_core->v__DOT__sdcard_controller__DOT__r_rsp_state);
|
|
printf(" LL[%d,%2x->CK=%d/%2x,%s,ST=%2d,TX=%2x,RX=%2x->%d,%2x] ",
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_stb,
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_dat,
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_z_counter,
|
|
// (m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter==0)?1:0,
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter,
|
|
(m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_idle)?"IDLE":" ",
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_state,
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_byte,
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_ireg,
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_stb,
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_dat
|
|
);
|
|
printf(" CRC=%02x/%2d",
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc,
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc_cnt);
|
|
printf(" SPI(%d,%d,%d/%d,%d)->?",
|
|
m_core->o_sf_cs_n,
|
|
m_core->o_sd_cs_n,
|
|
m_core->o_spi_sck, m_core->v__DOT__sdcard_sck,
|
|
m_core->o_spi_mosi);
|
|
|
|
printf(" CK=%d,LN=%d",
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
|
m_core->v__DOT__sdcard_controller__DOT__r_lgblklen);
|
|
|
|
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_use_fifo){
|
|
printf(" FIFO");
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_fifo_wr)
|
|
printf("-WR(%04x,%d,%d,%d)",
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_reg,
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_stb,
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_pkt_state,
|
|
m_core->v__DOT__sdcard_controller__DOT__r_have_data_response_token);
|
|
else
|
|
printf("-RD(%04x,%d,%d,%d)",
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_reg,
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_stb,
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_state,
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_complete
|
|
);
|
|
}
|
|
|
|
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_rd)
|
|
printf(" LL-RD");
|
|
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr)
|
|
printf(" LL-WR");
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_have_start_token)
|
|
printf(" START-TOK");
|
|
printf(" %3d/%02x",
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_addr,
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_byte&0x0ff);
|
|
*/
|
|
|
|
|
|
/*
|
|
printf(" DMAC[%d]: %08x/%08x/%08x(%03x) -- (%d,%d,%c)%c%c:@%08x-[%4d,%4d/%4d,%4d-#%4d]%08x",
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_waddr,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_raddr,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_len,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_blocklen_sub_one,
|
|
m_core->v__DOT__zippy__DOT__dc_cyc,
|
|
// m_core->v__DOT__zippy__DOT__dc_stb,
|
|
(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 2)?1:0,
|
|
|
|
((m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 4)
|
|
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 5)
|
|
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 6))?'W':'R',
|
|
//(m_core->v__DOT__zippy__DOT__dc_we)?'W':'R',
|
|
(m_core->v__DOT__zippy__DOT__dc_ack)?'A':' ',
|
|
(m_core->v__DOT__zippy__DOT__dc_stall)?'S':' ',
|
|
m_core->v__DOT__zippy__DOT__dc_addr,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__rdaddr,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nread,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nracks,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwacks,
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwritten,
|
|
m_core->v__DOT__zippy__DOT__dc_data);
|
|
|
|
printf(" %08x-PIC%08x",
|
|
m_core->v__DOT__zippy__DOT__main_int_vector,
|
|
m_core->v__DOT__zippy__DOT__pic_data);
|
|
*/
|
|
|
|
printf("\n"); fflush(stdout);
|
printf("\n"); fflush(stdout);
|
} m_last_writeout = writeout;
|
} m_last_writeout = writeout;
|
|
|
}
|
}
|
|
|
};
|
};
|
|
|
BUSMASTER_TB *tb;
|
BUSMASTER_TB *tb;
|
