| Line 38... |
Line 38... |
//
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//
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// #define UARTLEN 8681 // Minimum ticks per character, 115200 Baud
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// #define UARTLEN 8681 // Minimum ticks per character, 115200 Baud
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//
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//
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// At 4MBaud, each bit takes 25 clocks. 10 bits would thus take 250 clocks
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// At 4MBaud, each bit takes 25 clocks. 10 bits would thus take 250 clocks
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//
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//
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#define UARTLEN 250 // Minimum ticks per character, 4M Baud
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// #define UARTLEN 250 // Minimum ticks per character, 4M Baud
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// #define UARTLEN 1000 // Minimum ticks per character, 1M Hz
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// #define UARTLEN 8 // Minimum ticks per character
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// #define UARTLEN 8 // Minimum ticks per character
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#define UARTLEN 4096 //
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template <class VA> class PIPECMDR : public TESTB<VA> {
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template <class VA> class PIPECMDR : public TESTB<VA> {
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void setup_listener(const int port) {
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void setup_listener(const int port) {
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struct sockaddr_in my_addr;
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struct sockaddr_in my_addr;
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| Line 82... |
Line 84... |
}
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}
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public:
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public:
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int m_skt, m_con;
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int m_skt, m_con;
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char m_txbuf[PIPEBUFLEN], m_rxbuf[PIPEBUFLEN];
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char m_txbuf[PIPEBUFLEN], m_rxbuf[PIPEBUFLEN];
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int m_ilen, m_rxpos, m_txpos, m_uart_wait;
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int m_ilen, m_rxpos, m_txpos, m_uart_wait, m_tx_busy;
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bool m_started_flag;
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bool m_started_flag;
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PIPECMDR(const int port) : TESTB<VA>() {
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PIPECMDR(const int port) : TESTB<VA>() {
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m_con = m_skt = -1;
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m_con = m_skt = -1;
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setup_listener(port);
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setup_listener(port);
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m_rxpos = m_txpos = m_ilen = 0;
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m_rxpos = m_txpos = m_ilen = 0;
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m_started_flag = false;
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m_started_flag = false;
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m_uart_wait = 0;
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m_uart_wait = 0; // Flow control into the FPGA
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m_tx_busy = 0; // Flow control out of the FPGA
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}
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}
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virtual void kill(void) {
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virtual void kill(void) {
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// Close any active connection
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// Close any active connection
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if (m_con >= 0) close(m_con);
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if (m_con >= 0) close(m_con);
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Line 175... |
fflush(stdout);
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fflush(stdout);
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}
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}
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*/
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*/
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TESTB<VA>::tick();
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TESTB<VA>::tick();
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bool tx_accepted = false;
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if (m_tx_busy == 0) {
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if ((TESTB<VA>::m_core->o_tx_stb)&&(m_con > 0)) {
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if ((TESTB<VA>::m_core->o_tx_stb)&&(m_con > 0)) {
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m_txbuf[m_txpos++] = TESTB<VA>::m_core->o_tx_data;
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m_txbuf[m_txpos++] = TESTB<VA>::m_core->o_tx_data;
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tx_accepted = true;
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if ((TESTB<VA>::m_core->o_tx_data == '\n')||(m_txpos >= sizeof(m_txbuf))) {
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if ((TESTB<VA>::m_core->o_tx_data == '\n')||(m_txpos >= sizeof(m_txbuf))) {
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int snt = 0;
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int snt = 0;
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snt = send(m_con, m_txbuf, m_txpos, 0);
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snt = send(m_con, m_txbuf, m_txpos, 0);
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m_txbuf[m_txpos] = '\0';
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m_txbuf[m_txpos] = '\0';
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| Line 187... |
Line 193... |
snt);
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snt);
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}
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}
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m_txpos = 0;
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m_txpos = 0;
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}
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}
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}
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}
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} else
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m_tx_busy--;
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if ((TESTB<VA>::m_core->o_tx_stb)&&(TESTB<VA>::m_core->i_tx_busy==0))
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m_tx_busy = UARTLEN;
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TESTB<VA>::m_core->i_tx_busy = (m_tx_busy != 0);
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if (0) {
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if ((m_tx_busy!=0)||(TESTB<VA>::m_core->i_tx_busy)
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||(TESTB<VA>::m_core->o_tx_stb)
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||(tx_accepted))
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printf("%4d %d %d %02x %s\n",
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m_tx_busy,
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TESTB<VA>::m_core->i_tx_busy,
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TESTB<VA>::m_core->o_tx_stb,
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TESTB<VA>::m_core->o_tx_data,
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(tx_accepted)?"READ!":"");
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}
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/*
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/*
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if((TESTB<VA>::m_core->o_wb_cyc)||(TESTB<VA>::m_core->o_wb_stb)){
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if((TESTB<VA>::m_core->o_wb_cyc)||(TESTB<VA>::m_core->o_wb_stb)){
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printf("BUS: %d,%d,%d %8x %8x\n",
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printf("BUS: %d,%d,%d %8x %8x\n",
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TESTB<VA>::m_core->o_wb_cyc,
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TESTB<VA>::m_core->o_wb_cyc,
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