Subversion Repositories xulalx25soc

#define POWERED_UP_STATE        6

#define POWERED_UP_STATE        6

#define CLK_RATE_HZ             100000000 // = 100 MHz = 100 * 10^6

#define CLK_RATE_HZ             100000000 // = 100 MHz = 100 * 10^6

#define PWRUP_WAIT_CKS          ((int)(.000200 * CLK_RATE_HZ))

#define PWRUP_WAIT_CKS          ((int)(.000200 * CLK_RATE_HZ))

#define MAX_BANKOPEN_TIME       ((int)(.000100 * CLK_RATE_HZ))

#define MAX_BANKOPEN_TIME       ((int)(.000100 * CLK_RATE_HZ))

#define MAX_REFRESH_TIME        ((int)(.064 * CLK_RATE_HZ))

#define MAX_REFRESH_TIME        ((int)(.064 * CLK_RATE_HZ))

class   SDRAMSIM {

class   SDRAMSIM {

        int     m_pwrup;

        int     m_pwrup;

        short   *m_mem;

        short   *m_mem;

        short   m_last_value, m_qmem[4];

        short   m_last_value, m_qmem[4];

        int     m_bank_status[NBANKS];

        int     m_bank_status[NBANKS];

        int     m_bank_row[NBANKS];

        int     m_bank_row[NBANKS];

        int     m_bank_open_time[NBANKS];

        int     m_bank_open_time[NBANKS];

        unsigned        *m_refresh_time;

        unsigned        *m_refresh_time;

        int             m_refresh_loc, m_nrefresh;

        int             m_refresh_loc, m_nrefresh;

        int     m_clocks_till_idle;

        int     m_clocks_till_idle;

        bool    m_next_wr;

        bool    m_next_wr;

        unsigned        m_fail;

        unsigned        m_fail;

public:

public:

        SDRAMSIM(void) {

        SDRAMSIM(void) {

                m_last_value = 0;

                m_last_value = 0;

                m_clocks_till_idle = PWRUP_WAIT_CKS;

                m_clocks_till_idle = PWRUP_WAIT_CKS;

                m_wr_addr = 0;

                m_wr_addr = 0;

                m_qloc  = 0;

                m_qloc  = 0;

                m_next_wr = true;

                m_next_wr = true;

                m_fail = 0;

                m_fail = 0;

        }

        }