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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_1010</TT></TD><TH align=right>1</TH><TD>Receive UART RX value</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_1010</TT></TD><TH align=right>1</TH><TD>Receive UART RX value</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_1011</TT></TD><TH align=right>1</TH><TD>Transmit UART port</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_1011</TT></TD><TH align=right>1</TH><TD>Transmit UART port</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_11xx</TT></TD><TH align=right>4</TH><TD>Flash Control Words</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_11xx</TT></TD><TH align=right>4</TH><TD>Flash Control Words</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_0xxx</TT></TD><TH align=right>8</TH><TD>RTC Clock</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_0xxx</TT></TD><TH align=right>8</TH><TD>RTC Clock</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_1yyx</TT></TD><TH align=right>2</TH><TD>Scope #Y (0..3)</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_1yyx</TT></TD><TH align=right>2</TH><TD>Scope #Y (0..3)</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_0000</TT></TD><TH align=right>?</TH><TD>SD Card Control Register</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_00xx</TT></TD><TH align=right>4</TH><TD>SD Card Registers: Control, Data, FIFO zero and FIFO one</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_0001</TT></TD><TH align=right>?</TH><TD>SD Card Data Register</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_0010</TT></TD><TH align=right>?</TH><TD>SD Card FIFO zero</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_0011</TT></TD><TH align=right>?</TH><TD>SD Card FIFO one</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_01xx_xxxx</TT></TD><TH align=right>32</TH><TD>(ICAPE Access -- not yet proven)</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_01xx_xxxx</TT></TD><TH align=right>32</TH><TD>(ICAPE Access -- not yet proven)</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_001x_xxxx_xxxx_xxxx</TT></TD><TH align=right>8k</TH><TD>On Chip RAM</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_001x_xxxx_xxxx_xxxx</TT></TD><TH align=right>8k</TH><TD>On Chip RAM</TD></TR>
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<TR><TD align=right><TT>0_0000_01xx_xxxx_xxxx_xxxx_xxxx</TT></TD><TH align=right>256k</TH><TD>1 MB SPI Flash (256kW)</TD></TR>
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<TR><TD align=right><TT>0_0000_01xx_xxxx_xxxx_xxxx_xxxx</TT></TD><TH align=right>256k</TH><TD>1 MB SPI Flash (256kW)</TD></TR>
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<TR><TD align=right><TT>0_1rrr_rrrr_rrrr_rrbb_cccc_cccc</TT></TD><TH align=right>8M</TH><TD>32 MB SDRAM (8MW)</TD></TR>
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<TR><TD align=right><TT>0_1rrr_rrrr_rrrr_rrbb_cccc_cccc</TT></TD><TH align=right>8M</TH><TD>32 MB SDRAM (8MW)</TD></TR>
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<TR><TD align=right><TT>1_yyyy_yyyy_yyyy_yyyy_yyyy_yyyx</TT></TD><TH align=right>2</TH><TD>External Zip CPU control (y bits are don't cares, not accessible from ZipCPU)</TD></TR>
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<TR><TD align=right><TT>1_yyyy_yyyy_yyyy_yyyy_yyyy_yyyx</TT></TD><TH align=right>2</TH><TD>External Zip CPU control (y bits are don't cares, not accessible from ZipCPU)</TD></TR>
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