| Line 373... |
Line 373... |
// Addresses ...
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// Addresses ...
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// 0000 xxxx configuration/control registers
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// 0000 xxxx configuration/control registers
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// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
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// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
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// 1xxx xxxx Up-sampler taps
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// 1xxx xxxx Up-sampler taps
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// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
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// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
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`ifndef SPEEDY_IO
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wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
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wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
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assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
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assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
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assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
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assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
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assign io_sel = (io_bank)&&(pre_io);
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assign io_sel = (io_bank)&&(pre_io);
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assign pre_pwm = (wb_addr[4: 1]== 4'h4);
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assign pre_pwm = (wb_addr[4: 1]== 4'h4);
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| Line 395... |
Line 398... |
assign sdcard_sel=((wb_cyc)&&(wb_addr[31:2]== 30'h48));
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assign sdcard_sel=((wb_cyc)&&(wb_addr[31:2]== 30'h48));
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`else
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`else
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assign sdcard_sel=1'b0;
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assign sdcard_sel=1'b0;
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`endif
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`endif
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assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
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assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
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`else
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// While the following would make the bus infinitely easier to decode,
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// it would also scramble where everything on the bus is located at,
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// while also making it difficult to access these values via offsets
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// of a register. Further, while simpler, everything would alias all
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// over the place as well--that is, devices would show up at multiple
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// locations on the bus. It's all a tradeoff.
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assign iovec = { wb_addr[23],wb_addr[18],wb_addr[15:13] }
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assign sdram_sel =((wb_cyc)&&(io_vec[4]));
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assign flash_sel =((wb_cyc)&&(io_vec[4:3]==2'b01));
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assign mem_sel =((wb_cyc)&&(io_vec[4:0]==5'h07));
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assign cfg_sel =((wb_cyc)&&(io_vec[4:0]==5'h06));
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`ifdef SDCARD_ACCESS
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assign sdcard_sel=((wb_cyc)&&(io_vec[4:0]==5'h05));
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`else
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assign sdcard_sel=1'b0;
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`endif
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assign scop_sel =((wb_cyc)&&(io_vec[4:0]==5'h04));
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assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
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assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
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assign puf_sel =((wb_cyc)&&(io_vec[4:0]==5'h02));
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assign io_sel =((wb_cyc)&&(io_vec[4:0]==5'h01));
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assign wb_err =((wb_cyc)&&(io_vec[4:0]==5'h00));
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assign flctl_sel = (puf_sel)&&(wb_addr[3]);
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assign pwm_sel = (puf_sel)&&(wb_addr[3:2]==2'b00);
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// Note that in the following definition, the UART is given four words
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// despite the fact that it can probably only use 3.
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assign uart_sel = (puf_sel)&&(wb_addr[3:2]==2'b01);
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`endif
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assign none_sel =((wb_cyc)&&(wb_stb)&&(~
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assign none_sel =((wb_cyc)&&(wb_stb)&&(~
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(io_sel
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(io_sel
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||uart_sel
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||uart_sel
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||pwm_sel
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||pwm_sel
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| Line 438... |
Line 472... |
if (wb_err)
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if (wb_err)
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bus_err_addr <= wb_addr;
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bus_err_addr <= wb_addr;
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wire flash_interrupt, sdcard_interrupt, scop_interrupt,
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wire flash_interrupt, sdcard_interrupt, scop_interrupt,
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uart_rx_int, uart_tx_int, pwm_int;
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uart_rx_int, uart_tx_int, pwm_int;
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wire [(NGPO-1):0] w_gpio;
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// The I/O processor, herein called an ioslave
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// The I/O processor, herein called an ioslave
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ioslave #(NGPO, NGPI) runio(i_clk,
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ioslave #(NGPO, NGPI) runio(i_clk,
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wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
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wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
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wb_data, io_ack, io_stall, io_data,
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wb_data, io_ack, io_stall, io_data,
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i_gpio, o_gpio,
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i_gpio, w_gpio,
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bus_err_addr,
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bus_err_addr,
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{
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{
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sdcard_interrupt,
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sdcard_interrupt,
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uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
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uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
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flash_interrupt,
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flash_interrupt,
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| Line 482... |
Line 517... |
// sample rate to get the first parameter for the PWM device. The
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// sample rate to get the first parameter for the PWM device. The
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// second parameter is zero or one, indicating whether or not the
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// second parameter is zero or one, indicating whether or not the
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// audio rate can be adjusted (1), or whether it is fixed within the
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// audio rate can be adjusted (1), or whether it is fixed within the
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// build (0).
|
// build (0).
|
`ifdef XULA25
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`ifdef XULA25
|
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`define FMHACK
|
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|
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`ifdef FMHACK
|
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wbfmtxhack #(16'd1813) // 44.1 kHz, user adjustable
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`else
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wbpwmaudio #(16'd1813,1) // 44.1 kHz, user adjustable
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wbpwmaudio #(16'd1813,1) // 44.1 kHz, user adjustable
|
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`endif
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`else
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`else
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wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate
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wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate
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`endif
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`endif
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pwmdev(i_clk,
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pwmdev(i_clk,
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wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
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wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
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wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
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wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
|
|
|
|
`ifdef FMHACK
|
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assign o_gpio = {(NGPO){o_pwm}};
|
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`else
|
|
assign o_gpio = w_gpio;
|
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`endif
|
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|
|
|
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//
|
//
|
// FLASH MEMORY CONFIGURATION ACCESS
|
// FLASH MEMORY CONFIGURATION ACCESS
|
//
|
//
|
wire flash_cs_n, flash_sck, flash_mosi;
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wire flash_cs_n, flash_sck, flash_mosi;
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