| Line 102... |
Line 102... |
// `define SDRAM_SCOPE
|
// `define SDRAM_SCOPE
|
// `define UART_SCOPE
|
// `define UART_SCOPE
|
//
|
//
|
// Position #4: The Zip CPU scope
|
// Position #4: The Zip CPU scope
|
//
|
//
|
|
`ifdef INCLUDE_ZIPCPU
|
|
`ifdef VERILATOR
|
|
`define ZIP_SCOPE
|
|
`else // VERILATOR
|
`ifdef XULA25
|
`ifdef XULA25
|
// `define ZIP_SCOPE
|
`define ZIP_SCOPE
|
`endif
|
`endif // XULA25
|
|
`endif // VERILATOR
|
|
`endif // INCLUDE_ZIPCPU
|
|
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
// The SPI Flash lines
|
// The SPI Flash lines
|
o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
|
o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
|
| Line 206... |
Line 212... |
wire zip_ack, zip_stall, zip_err;
|
wire zip_ack, zip_stall, zip_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire [31:0] dwb_addr, dwb_odata;
|
wire [31:0] dwb_addr, dwb_odata;
|
wire [8:0] w_ints_to_zip_cpu;
|
wire [8:0] w_ints_to_zip_cpu;
|
`ifdef INCLUDE_ZIPCPU
|
`ifdef INCLUDE_ZIPCPU
|
`ifdef XULA25
|
`ifdef ZIP_SCOPE
|
wire [31:0] zip_debug;
|
wire [31:0] zip_debug;
|
zipsystem #(24'h2000,ZA,9,1,9)
|
`endif
|
|
`ifdef XULA25
|
|
zipsystem #(24'h2000,ZA,10,1,9)
|
zippy(i_clk, 1'b0,
|
zippy(i_clk, 1'b0,
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
w_ints_to_zip_cpu, zip_cpu_int,
|
w_ints_to_zip_cpu, zip_cpu_int,
|
// Debug wishbone interface
|
// Debug wishbone interface
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
wbu_data,
|
wbu_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
zip_debug);
|
`ifdef ZIP_SCOPE
|
|
, zip_debug
|
|
`endif
|
|
);
|
`else
|
`else
|
zipbones #(24'h2000,ZA,8,1)
|
zipbones #(24'h2000,ZA,8,1)
|
zippy(i_clk, 1'b0,
|
zippy(i_clk, 1'b0,
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
| Line 231... |
Line 242... |
w_interrupt, zip_cpu_int,
|
w_interrupt, zip_cpu_int,
|
// Debug wishbone interface
|
// Debug wishbone interface
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
wbu_data,
|
wbu_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
|
`ifdef ZIP_SCOPE
|
|
, zip_debug
|
|
`endif
|
|
);
|
`endif
|
`endif
|
generate
|
generate
|
if (ZA < 32)
|
if (ZA < 32)
|
assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
|
assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
|
else
|
else
|
| Line 366... |
Line 381... |
: ((uart_ack|pwm_ack)?((uart_ack)?uart_data: pwm_data)
|
: ((uart_ack|pwm_ack)?((uart_ack)?uart_data: pwm_data)
|
: ((cfg_ack) ? cfg_data
|
: ((cfg_ack) ? cfg_data
|
: ((sdram_ack|sdcard_ack)
|
: ((sdram_ack|sdcard_ack)
|
?((sdram_ack)? sdram_data : sdcard_data)
|
?((sdram_ack)? sdram_data : sdcard_data)
|
: ((mem_ack)?mem_data:flash_data)))); // if (flash_ack)
|
: ((mem_ack)?mem_data:flash_data)))); // if (flash_ack)
|
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
|
assign wb_err = ((wb_stb)&&(none_sel || many_sel))
|
|
|| ((wb_cyc)&&(many_ack));
|
|
|
// Addresses ...
|
// Addresses ...
|
// 0000 xxxx configuration/control registers
|
// 0000 xxxx configuration/control registers
|
// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
|
// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
|
// 1xxx xxxx Up-sampler taps
|
// 1xxx xxxx Up-sampler taps
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
|
|
|
`define SPEEDY_IO
|
`ifndef SPEEDY_IO
|
`ifndef SPEEDY_IO
|
|
|
wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
|
wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
|
assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
|
assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
|
assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
|
assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
|
| Line 399... |
Line 416... |
`else
|
`else
|
assign sdcard_sel=1'b0;
|
assign sdcard_sel=1'b0;
|
`endif
|
`endif
|
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
|
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
|
`else
|
`else
|
// While the following would make the bus infinitely easier to decode,
|
wire [3:0] iovec;
|
// it would also scramble where everything on the bus is located at,
|
assign iovec = { wb_addr[23],wb_addr[18],wb_addr[13],wb_addr[8] };
|
// while also making it difficult to access these values via offsets
|
|
// of a register. Further, while simpler, everything would alias all
|
assign sdram_sel = (iovec[3]);
|
// over the place as well--that is, devices would show up at multiple
|
assign flash_sel = (iovec[3:2]==2'b01);
|
// locations on the bus. It's all a tradeoff.
|
assign mem_sel = (iovec[3:1]==3'b001);
|
assign iovec = { wb_addr[23],wb_addr[18],wb_addr[15:13] }
|
assign io_bank = (iovec[3:0]==4'b0001)&&(wb_addr[7:5]==3'b000);
|
|
assign cfg_sel = (iovec[3:0]==4'b0001)&&(wb_addr[6]);
|
assign sdram_sel =((wb_cyc)&&(io_vec[4]));
|
assign sdcard_sel= (iovec[3:0]==4'b0001)&&(wb_addr[6:5]==2'b01);
|
assign flash_sel =((wb_cyc)&&(io_vec[4:3]==2'b01));
|
assign scop_sel = (io_bank)&&(wb_addr[7:3]==5'b00011);
|
assign mem_sel =((wb_cyc)&&(io_vec[4:0]==5'h07));
|
assign io_sel = (io_bank)&&(wb_addr[7:5]==3'b000)
|
assign cfg_sel =((wb_cyc)&&(io_vec[4:0]==5'h06));
|
&&(wb_addr[4:0] != 5'b00111) // Not UART Ctrl
|
`ifdef SDCARD_ACCESS
|
&&(wb_addr[3] != 1'b1);//Not PWM/UART/Flash/Scp
|
assign sdcard_sel=((wb_cyc)&&(io_vec[4:0]==5'h05));
|
assign flctl_sel = (io_bank)&&(wb_addr[4:2]==3'b011);
|
`else
|
assign pwm_sel = (io_bank)&&(wb_addr[4:1]==4'b0100);
|
assign sdcard_sel=1'b0;
|
|
`endif
|
|
assign scop_sel =((wb_cyc)&&(io_vec[4:0]==5'h04));
|
|
assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
|
|
assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
|
|
assign puf_sel =((wb_cyc)&&(io_vec[4:0]==5'h02));
|
|
assign io_sel =((wb_cyc)&&(io_vec[4:0]==5'h01));
|
|
assign wb_err =((wb_cyc)&&(io_vec[4:0]==5'h00));
|
|
assign flctl_sel = (puf_sel)&&(wb_addr[3]);
|
|
assign pwm_sel = (puf_sel)&&(wb_addr[3:2]==2'b00);
|
|
// Note that in the following definition, the UART is given four words
|
// Note that in the following definition, the UART is given four words
|
// despite the fact that it can probably only use 3.
|
// despite the fact that it can probably only use 3.
|
assign uart_sel = (puf_sel)&&(wb_addr[3:2]==2'b01);
|
assign uart_sel = (io_bank)&&((wb_addr[4:1]==4'b0101)
|
|
||(wb_addr[4:0]==5'b00111));
|
|
|
`endif
|
`endif
|
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(~
|
assign none_sel =((wb_stb)&&(~
|
(io_sel
|
(io_sel
|
||uart_sel
|
||uart_sel
|
||pwm_sel
|
||pwm_sel
|
||flctl_sel
|
||flctl_sel
|
||scop_sel
|
||scop_sel
|
||cfg_sel
|
||cfg_sel
|
||mem_sel
|
||mem_sel
|
||sdram_sel
|
||sdram_sel
|
||sdcard_sel
|
||sdcard_sel
|
||flash_sel)));
|
||flash_sel)));
|
assign many_sel =((wb_cyc)&&(wb_stb)&&(
|
assign many_sel =((wb_stb)&&(
|
{3'h0, io_sel}
|
{3'h0, io_sel}
|
+{3'h0, uart_sel}
|
+{3'h0, uart_sel}
|
+{3'h0, pwm_sel}
|
+{3'h0, pwm_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, scop_sel}
|
+{3'h0, scop_sel}
|
| Line 517... |
Line 525... |
// sample rate to get the first parameter for the PWM device. The
|
// sample rate to get the first parameter for the PWM device. The
|
// second parameter is zero or one, indicating whether or not the
|
// second parameter is zero or one, indicating whether or not the
|
// audio rate can be adjusted (1), or whether it is fixed within the
|
// audio rate can be adjusted (1), or whether it is fixed within the
|
// build (0).
|
// build (0).
|
`ifdef XULA25
|
`ifdef XULA25
|
`define FMHACK
|
// `define FMHACK
|
|
|
`ifdef FMHACK
|
`ifdef FMHACK
|
wbfmtxhack #(16'd1813) // 44.1 kHz, user adjustable
|
wbfmtxhack #(16'd1813) // 44.1 kHz, user adjustable
|
`else
|
`else
|
wbpwmaudio #(16'd1813,1) // 44.1 kHz, user adjustable
|
wbpwmaudio #(16'd1813,1,16) // 44.1 kHz, user adjustable
|
`endif
|
`endif
|
|
|
`else
|
`else
|
wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate
|
wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate
|
`endif
|
`endif
|
| Line 556... |
Line 564... |
flash_interrupt, flash_grant);
|
flash_interrupt, flash_grant);
|
`else
|
`else
|
reg r_flash_ack;
|
reg r_flash_ack;
|
initial r_flash_ack = 1'b0;
|
initial r_flash_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_flash_ack <= (wb_cyc)&&(wb_stb)&&((flash_sel)||(flctl_sel));
|
r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
|
|
|
assign flash_ack = r_flash_ack;
|
assign flash_ack = r_flash_ack;
|
assign flash_stall = 1'b0;
|
assign flash_stall = 1'b0;
|
assign flash_data = 32'h0000;
|
assign flash_data = 32'h0000;
|
assign flash_interrupt = 1'b0;
|
assign flash_interrupt = 1'b0;
|
| Line 586... |
Line 594... |
sdcard_interrupt, sdcard_grant, sdspi_scope);
|
sdcard_interrupt, sdcard_grant, sdspi_scope);
|
`else
|
`else
|
reg r_sdcard_ack;
|
reg r_sdcard_ack;
|
initial r_sdcard_ack = 1'b0;
|
initial r_sdcard_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_sdcard_ack <= (wb_cyc)&&(wb_stb)&&(sdcard_sel);
|
r_sdcard_ack <= (wb_stb)&&(sdcard_sel);
|
assign sdcard_stall = 1'b0;
|
assign sdcard_stall = 1'b0;
|
assign sdcard_ack = r_sdcard_ack;
|
assign sdcard_ack = r_sdcard_ack;
|
assign sdcard_data = 32'h0000;
|
assign sdcard_data = 32'h0000;
|
assign sdcard_interrupt= 1'b0;
|
assign sdcard_interrupt= 1'b0;
|
`endif // SDCARD_ACCESS
|
`endif // SDCARD_ACCESS
|
| Line 652... |
Line 660... |
`else
|
`else
|
assign cfg_scope = 32'h0000;
|
assign cfg_scope = 32'h0000;
|
reg r_cfg_ack;
|
reg r_cfg_ack;
|
initial r_cfg_ack = 1'b0;
|
initial r_cfg_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_cfg_ack <= ((wb_cyc)&&(cfg_sel)&&(wb_stb)&&(~cfg_stall));
|
r_cfg_ack <= ((cfg_sel)&&(wb_stb)&&(~cfg_stall));
|
assign cfg_ack = r_cfg_ack;
|
assign cfg_ack = r_cfg_ack;
|
assign cfg_stall = 1'b0;
|
assign cfg_stall = 1'b0;
|
assign cfg_data = 32'h0000;
|
assign cfg_data = 32'h0000;
|
`endif
|
`endif
|
|
|
| Line 668... |
Line 676... |
memdev #(13) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
memdev #(13) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
wb_addr[12:0], wb_data, mem_ack, mem_stall, mem_data);
|
wb_addr[12:0], wb_data, mem_ack, mem_stall, mem_data);
|
`else
|
`else
|
reg r_mem_ack;
|
reg r_mem_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_mem_ack = (wb_cyc)&&(wb_stb)&&(mem_sel);
|
r_mem_ack = (wb_stb)&&(mem_sel);
|
assign mem_data = 32'h000;
|
assign mem_data = 32'h000;
|
assign mem_stall = 1'b0;
|
assign mem_stall = 1'b0;
|
assign mem_ack = r_mem_ack;
|
assign mem_ack = r_mem_ack;
|
`endif
|
`endif
|
|
|
| Line 692... |
Line 700... |
sdram_debug);
|
sdram_debug);
|
`else
|
`else
|
reg r_sdram_ack;
|
reg r_sdram_ack;
|
initial r_sdram_ack = 1'b0;
|
initial r_sdram_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_sdram_ack <= (wb_cyc)&&(wb_stb)&&(sdram_sel);
|
r_sdram_ack <= (wb_stb)&&(sdram_sel);
|
assign sdram_ack = r_sdram_ack;
|
assign sdram_ack = r_sdram_ack;
|
assign sdram_stall = 1'b0;
|
assign sdram_stall = 1'b0;
|
assign sdram_data = 32'h0000;
|
assign sdram_data = 32'h0000;
|
|
|
assign o_ram_ce_n = 1'b1;
|
assign o_ram_ce_n = 1'b1;
|
| Line 754... |
Line 762... |
|
|
wire [31:0] scop_cfg_data;
|
wire [31:0] scop_cfg_data;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
`ifdef CFG_SCOPE
|
`ifdef CFG_SCOPE
|
wire scop_cfg_trigger;
|
wire scop_cfg_trigger;
|
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
|
assign scop_cfg_trigger = (wb_stb)&&(cfg_sel);
|
wbscope #(5'h7) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
wbscope #(5'h7) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_interrupt);
|
scop_cfg_interrupt);
|
`else
|
`else
|
`ifdef SDCARD_SCOPE
|
`ifdef SDCARD_SCOPE
|
wire scop_sd_trigger, scop_sd_ce;
|
wire scop_sd_trigger, scop_sd_ce;
|
assign scop_sd_trigger = (wb_cyc)&&(wb_stb)&&(sdcard_sel)&&(wb_we);
|
assign scop_sd_trigger = (wb_stb)&&(sdcard_sel)&&(wb_we);
|
assign scop_sd_ce = 1'b1; // sdspi_scope[31];
|
assign scop_sd_ce = 1'b1; // sdspi_scope[31];
|
wbscope #(5'h9) sdspiscope(i_clk, scop_sd_ce,
|
wbscope #(5'h9) sdspiscope(i_clk, scop_sd_ce,
|
scop_sd_trigger, sdspi_scope,
|
scop_sd_trigger, sdspi_scope,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
| Line 817... |
Line 825... |
`endif
|
`endif
|
|
|
wire [31:0] scop_zip_data;
|
wire [31:0] scop_zip_data;
|
wire scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
|
wire scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
|
`ifdef ZIP_SCOPE
|
`ifdef ZIP_SCOPE
|
wire zip_trigger;
|
reg zip_trigger, pre_trigger_a, pre_trigger_b;
|
assign zip_trigger=(wbu_zip_sel)&&(wbu_we)&&(wbu_stb)&&(~wbu_addr[0]);
|
always @(posedge i_clk)
|
|
begin
|
|
pre_trigger_a <= (wb_stb)&&(wb_addr[31:0]==32'h010b);
|
|
pre_trigger_b <= (|wb_data[31:8]);
|
|
zip_trigger= (pre_trigger_a)&&(pre_trigger_b)||(zip_debug[31]);
|
|
end
|
wbscope #(5'h9) zipscope(i_clk, 1'b1, zip_trigger,
|
wbscope #(5'h9) zipscope(i_clk, 1'b1, zip_trigger,
|
zip_debug,
|
zip_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
