| Line 43... |
Line 43... |
// `define NO_ZIP_WBU_DELAY
|
// `define NO_ZIP_WBU_DELAY
|
`define IMPLEMENT_ONCHIP_RAM
|
`define IMPLEMENT_ONCHIP_RAM
|
`define FANCY_ICAP_ACCESS
|
`define FANCY_ICAP_ACCESS
|
`define FLASH_ACCESS
|
`define FLASH_ACCESS
|
// `define FLASH_SCOPE
|
// `define FLASH_SCOPE
|
// `define CFG_SCOPE
|
`define CFG_SCOPE
|
`define SDRAM_SCOPE
|
// `define SDRAM_SCOPE
|
`define ZIP_SCOPE
|
`define ZIP_SCOPE
|
// `define SDCARD_ACCESS
|
// `define SDCARD_ACCESS
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
// The SPI Flash lines
|
// The SPI Flash lines
|
| Line 113... |
Line 113... |
wire [31:0] wbu_idata;
|
wire [31:0] wbu_idata;
|
// And then headed back home
|
// And then headed back home
|
wire w_interrupt;
|
wire w_interrupt;
|
// Oh, and the debug control for the ZIP CPU
|
// Oh, and the debug control for the ZIP CPU
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]);
|
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]));
|
wire [31:0] zip_dbg_data;
|
wire [31:0] zip_dbg_data;
|
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
|
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
`ifdef INCLUDE_ZIPCPU
|
`ifdef INCLUDE_ZIPCPU
|
((~wbu_zip_sel)&&(wbu_ack))
|
((~wbu_zip_sel)&&(wbu_ack))
|
| Line 362... |
Line 362... |
//
|
//
|
// UART device
|
// UART device
|
//
|
//
|
uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
|
uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
|
wb_cyc, (wb_stb)&&(uart_sel), wb_we,
|
wb_cyc, (wb_stb)&&(uart_sel), wb_we,
|
{ ~wb_addr[2], wb_addr[0]},
|
{ ~wb_addr[2], wb_addr[0]}, wb_data,
|
wb_data, uart_ack, uart_stall, uart_data,
|
uart_ack, uart_stall, uart_data,
|
uart_rx_int, uart_tx_int);
|
uart_rx_int, uart_tx_int);
|
|
|
//
|
//
|
// PWM (audio) device
|
// PWM (audio) device
|
//
|
//
|
| Line 572... |
Line 572... |
r_trigger <= 1'b1;
|
r_trigger <= 1'b1;
|
else
|
else
|
r_trigger <= 1'b0;
|
r_trigger <= 1'b0;
|
*/
|
*/
|
|
|
wbscope #(5'hd) sdramscope(i_clk, 1'b1, sdram_trigger,
|
wbscope #(5'ha) sdramscope(i_clk, 1'b1, sdram_trigger,
|
sdram_debug,
|
sdram_debug,
|
// zip_debug,
|
// zip_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
| Line 592... |
Line 592... |
wire [31:0] scop_zip_data;
|
wire [31:0] scop_zip_data;
|
wire scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
|
wire scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
|
`ifdef ZIP_SCOPE
|
`ifdef ZIP_SCOPE
|
wire zip_trigger;
|
wire zip_trigger;
|
assign zip_trigger=(wbu_zip_sel)&&(wbu_we)&&(wbu_stb)&&(~wbu_addr[0]);
|
assign zip_trigger=(wbu_zip_sel)&&(wbu_we)&&(wbu_stb)&&(~wbu_addr[0]);
|
wbscope #(5'hd) zipscope(i_clk, 1'b1, zip_trigger,
|
wbscope #(5'ha) zipscope(i_clk, 1'b1, zip_trigger,
|
zip_debug,
|
zip_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
scop_zip_ack, scop_zip_stall, scop_zip_data,
|
scop_zip_ack, scop_zip_stall, scop_zip_data,
|
