| Line 42... |
Line 42... |
`define INCLUDE_ZIPCPU
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`define INCLUDE_ZIPCPU
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// `define NO_ZIP_WBU_DELAY
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// `define NO_ZIP_WBU_DELAY
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`define IMPLEMENT_ONCHIP_RAM
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`define IMPLEMENT_ONCHIP_RAM
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`define FANCY_ICAP_ACCESS
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`define FANCY_ICAP_ACCESS
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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// `define SDCARD_ACCESS // Not built yet ...
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//
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//
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// `define FLASH_SCOPE
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// `define FLASH_SCOPE
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`ifdef FANCY_ICAP_ACCESS
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`define CFG_SCOPE
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`define CFG_SCOPE
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`endif
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// `define SDRAM_SCOPE
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// `define SDRAM_SCOPE
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`define ZIP_SCOPE
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`define ZIP_SCOPE
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// `define SDCARD_ACCESS
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module busmaster(i_clk, i_rst,
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module busmaster(i_clk, i_rst,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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// The SPI Flash lines
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// The SPI Flash lines
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o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
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o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
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// The SDRAM lines
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// The SDRAM lines
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| Line 537... |
Line 541... |
wire [31:0] scop_cfg_data;
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wire [31:0] scop_cfg_data;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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`ifdef CFG_SCOPE
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`ifdef CFG_SCOPE
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wire scop_cfg_trigger;
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wire scop_cfg_trigger;
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assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
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assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
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wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
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wbscope #(5'h7) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
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// Wishbone interface
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// Wishbone interface
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i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
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i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
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wb_we, wb_addr[0], wb_data,
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wb_we, wb_addr[0], wb_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_interrupt);
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scop_cfg_interrupt);
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