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Line 37... |
// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// `define XULA25
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`define INCLUDE_ZIPCPU
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`define INCLUDE_ZIPCPU
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// `define NO_ZIP_WBU_DELAY
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// `define NO_ZIP_WBU_DELAY
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`define IMPLEMENT_ONCHIP_RAM
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`define IMPLEMENT_ONCHIP_RAM
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`ifndef VERILATOR
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`ifndef XULA25
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`define FANCY_ICAP_ACCESS
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`define FANCY_ICAP_ACCESS
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`endif
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`endif
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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// `define SDCARD_ACCESS // Not built yet ...
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// `define SDCARD_ACCESS // Not built yet ...
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//
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//
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//
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//
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// `define FLASH_SCOPE
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// `define FLASH_SCOPE
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`ifdef FANCY_ICAP_ACCESS
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`ifdef FANCY_ICAP_ACCESS
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`define CFG_SCOPE
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`define CFG_SCOPE
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`endif
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`endif
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// `define SDRAM_SCOPE
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// `define SDRAM_SCOPE
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`ifdef XULA25
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`define ZIP_SCOPE
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`define ZIP_SCOPE
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`endif
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module busmaster(i_clk, i_rst,
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module busmaster(i_clk, i_rst,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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// The SPI Flash lines
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// The SPI Flash lines
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o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
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o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
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// The SDRAM lines
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// The SDRAM lines
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Line 158... |
wire zip_ack, zip_stall, zip_err;
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wire zip_ack, zip_stall, zip_err;
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wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
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wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
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wire [31:0] dwb_addr, dwb_odata;
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wire [31:0] dwb_addr, dwb_odata;
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wire [7:0] w_ints_to_zip_cpu;
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wire [7:0] w_ints_to_zip_cpu;
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`ifdef INCLUDE_ZIPCPU
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`ifdef INCLUDE_ZIPCPU
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`ifdef XULA25
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wire [31:0] zip_debug;
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wire [31:0] zip_debug;
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zipsystem #(24'h2000,ZA,8,1,8)
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zipsystem #(24'h2000,ZA,8,1,8)
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zippy(i_clk, 1'b0,
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zippy(i_clk, 1'b0,
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// Zippys wishbone interface
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// Zippys wishbone interface
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zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
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zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
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| Line 162... |
Line 172... |
((wbu_cyc)&&(wbu_zip_sel)),
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((wbu_cyc)&&(wbu_zip_sel)),
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((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
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((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
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wbu_data,
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wbu_data,
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zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
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zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
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zip_debug);
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zip_debug);
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`else
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zipbones #(24'h2000,ZA,8,1)
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zippy(i_clk, 1'b0,
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// Zippys wishbone interface
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zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
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zip_ack, zip_stall, dwb_idata, zip_err,
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w_interrupt, zip_cpu_int,
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// Debug wishbone interface
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((wbu_cyc)&&(wbu_zip_sel)),
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((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
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wbu_data,
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zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
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`endif
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generate
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generate
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if (ZA < 32)
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if (ZA < 32)
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assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
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assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
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else
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else
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assign zip_addr = w_zip_addr;
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assign zip_addr = w_zip_addr;
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Line 325... |
// Addresses ...
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// Addresses ...
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// 0000 xxxx configuration/control registers
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// 0000 xxxx configuration/control registers
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// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
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// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
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// 1xxx xxxx Up-sampler taps
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// 1xxx xxxx Up-sampler taps
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// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
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// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
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`ifndef SPEEDY_IO
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wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
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assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
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assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
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assign io_sel = (io_bank)&&(~flctl_sel)
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assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
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&&(~pwm_sel)&&(~uart_sel)&&(~scop_sel);
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assign io_sel = (io_bank)&&(pre_io);
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assign pwm_sel =((io_bank)&&(wb_addr[4: 1]== 4'h4));
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assign pre_pwm = (wb_addr[4: 1]== 4'h4);
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assign uart_sel =((io_bank)&&((wb_addr[4:1]== 4'h5)||(wb_addr[4:0]==5'h7)));
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assign pwm_sel = (io_bank)&&(pre_pwm);
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assign flctl_sel=((io_bank)&&(wb_addr[4: 2]== 3'h3));
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assign pre_uart = (wb_addr[4: 1]== 4'h5)||(wb_addr[4:0]==5'h7);
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assign scop_sel =((io_bank)&&(wb_addr[4: 3]== 2'h3));
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assign uart_sel = (io_bank)&&(pre_uart);
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assign pre_flctl= (wb_addr[4: 2]== 3'h3);
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assign flctl_sel= (io_bank)&&(pre_flctl);
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assign pre_scop = (wb_addr[4: 3]== 2'h3);
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assign scop_sel = (io_bank)&&(pre_scop);
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assign cfg_sel =((wb_cyc)&&(wb_addr[31: 6]== 26'h05));
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assign cfg_sel =((wb_cyc)&&(wb_addr[31: 6]== 26'h05));
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// zip_sel is not on the bus at this point
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// zip_sel is not on the bus at this point
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assign mem_sel =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
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assign mem_sel =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
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assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
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assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
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assign sdcard_sel=1'b0;
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assign sdcard_sel=1'b0;
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assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
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assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
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assign none_sel =((wb_cyc)&&(wb_stb)&&(~(io_sel||flctl_sel||scop_sel||cfg_sel||mem_sel||sdram_sel||sdcard_sel||flash_sel)));
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`else
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assign iovec = { wb_addr[23],wb_addr[18],wb_addr[15:13] }
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assign sdram_sel =((wb_cyc)&&(io_vec[4]));
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assign flash_sel =((wb_cyc)&&(io_vec[4:3]==2'b01));
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assign mem_sel =((wb_cyc)&&(io_vec[4:0]==5'h07));
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assign cfg_sel =((wb_cyc)&&(io_vec[4:0]==5'h06));
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assign sdcard_sel=((wb_cyc)&&(io_vec[4:0]==5'h05));
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assign scop_sel =((wb_cyc)&&(io_vec[4:0]==5'h04));
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assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
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assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
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assign puf_sel =((wb_cyc)&&(io_vec[4:0]==5'h02));
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assign io_sel =((wb_cyc)&&(io_vec[4:0]==5'h01));
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assign wb_err =((wb_cyc)&&(io_vec[4:0]==5'h00));
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assign flctl_sel = (puf_sel)&&(wb_addr[2]);
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assign pwm_sel = (puf_sel)&&(wb_addr[2:1]==2'b01);
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assign sdcard_sel=1'b0;//((wb_cyc)&&({wb_addr[23],wb_addr[18]}==2'b01));
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`endif
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assign none_sel =((wb_cyc)&&(wb_stb)&&(~
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(io_sel
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||uart_sel
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||pwm_sel
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||flctl_sel
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||scop_sel
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||cfg_sel
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||mem_sel
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||sdram_sel
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||sdcard_sel
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||flash_sel)));
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assign many_sel =((wb_cyc)&&(wb_stb)&&(
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assign many_sel =((wb_cyc)&&(wb_stb)&&(
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{3'h0, io_sel}
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{3'h0, io_sel}
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+{3'h0, uart_sel}
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+{3'h0, uart_sel}
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+{3'h0, pwm_sel}
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+{3'h0, pwm_sel}
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+{3'h0, flctl_sel}
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+{3'h0, flctl_sel}
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| Line 333... |
Line 393... |
wire many_ack;
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wire many_ack;
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assign many_ack =((wb_cyc)&&(
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assign many_ack =((wb_cyc)&&(
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{3'h0, io_ack}
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{3'h0, io_ack}
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+{3'h0, uart_ack}
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+{3'h0, uart_ack}
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+{3'h0, pwm_ack}
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+{3'h0, pwm_ack}
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// FLCTL acks through the flash, so one less check here
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+{3'h0, scop_ack}
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+{3'h0, scop_ack}
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+{3'h0, cfg_ack}
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+{3'h0, cfg_ack}
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+{3'h0, mem_ack}
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+{3'h0, mem_ack}
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+{3'h0, sdram_ack}
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+{3'h0, sdram_ack}
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+{3'h0, sdcard_ack}
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+{3'h0, sdcard_ack}
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| Line 353... |
Line 414... |
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
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wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
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wb_data, io_ack, io_stall, io_data,
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wb_data, io_ack, io_stall, io_data,
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i_gpio, o_gpio,
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i_gpio, o_gpio,
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bus_err_addr,
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bus_err_addr,
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{ uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
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{ uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
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flash_interrupt, zip_cpu_int },
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flash_interrupt,
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`ifdef XULA25
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zip_cpu_int
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`else
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1'b0
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`endif
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},
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w_ints_to_zip_cpu,
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w_ints_to_zip_cpu,
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w_interrupt);
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w_interrupt);
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// 8684
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// 8684
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// 1'bx, 4'h0, scop_sel, scop_ack, ~scop_stall,
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// 1'bx, 4'h0, scop_sel, scop_ack, ~scop_stall,
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// wb_err, ~vga_interrupt, 2'b00, flash_interrupt
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// wb_err, ~vga_interrupt, 2'b00, flash_interrupt
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