| Line 1... |
Line 1... |
|
`define XULA25
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Filename: busmaster.v
|
// Filename: busmaster.v
|
//
|
//
|
// Project: XuLA2 board
|
// Project: XuLA2 board
|
| Line 37... |
Line 38... |
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
|
//
|
//
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// `define XULA25
|
|
|
|
|
//
|
|
// Configuration question #1
|
|
//
|
|
// What innate capabilities are built into the board?
|
|
//
|
`define INCLUDE_ZIPCPU
|
`define INCLUDE_ZIPCPU
|
// `define NO_ZIP_WBU_DELAY
|
// `define NO_ZIP_WBU_DELAY
|
`define IMPLEMENT_ONCHIP_RAM
|
`define IMPLEMENT_ONCHIP_RAM
|
`ifndef VERILATOR
|
`ifndef VERILATOR
|
`ifndef XULA25
|
`ifndef XULA25
|
| Line 50... |
Line 55... |
`endif
|
`endif
|
`endif
|
`endif
|
`define FLASH_ACCESS
|
`define FLASH_ACCESS
|
// `define SDCARD_ACCESS // Not built yet ...
|
// `define SDCARD_ACCESS // Not built yet ...
|
//
|
//
|
|
|
|
|
|
//
|
|
// Configuration question #2
|
|
//
|
|
// Are any scopes built in to the board?
|
|
//
|
|
|
|
//
|
|
// Position #1: The flash scope, or perhaps the wishbone bus/uart/jtag scope
|
//
|
//
|
// `define FLASH_SCOPE
|
// `define FLASH_SCOPE
|
|
`ifndef FLASH_SCOPE
|
|
// `define WBUS_SCOPE // Occupies the FLASH_SCOPE location, so both cannot be active
|
|
`endif
|
|
//
|
|
// Position #2: The ICAP configuration scope
|
|
//
|
`ifdef FANCY_ICAP_ACCESS
|
`ifdef FANCY_ICAP_ACCESS
|
`define CFG_SCOPE
|
`define CFG_SCOPE // Only defined if we have the access ...
|
`endif
|
`endif
|
// `define SDRAM_SCOPE
|
//
|
|
// Position #3: The SDRAM scope
|
|
//
|
|
`define SDRAM_SCOPE
|
|
//
|
|
// Position #4: The Zip CPU scope
|
|
//
|
`ifdef XULA25
|
`ifdef XULA25
|
`define ZIP_SCOPE
|
// `define ZIP_SCOPE
|
`endif
|
`endif
|
|
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
// The SPI Flash lines
|
// The SPI Flash lines
|
| Line 326... |
Line 353... |
// 0000 xxxx configuration/control registers
|
// 0000 xxxx configuration/control registers
|
// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
|
// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
|
// 1xxx xxxx Up-sampler taps
|
// 1xxx xxxx Up-sampler taps
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
|
|
`ifndef SPEEDY_IO
|
|
|
|
wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
|
wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
|
assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
|
assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
|
assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
|
assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
|
assign io_sel = (io_bank)&&(pre_io);
|
assign io_sel = (io_bank)&&(pre_io);
|
assign pre_pwm = (wb_addr[4: 1]== 4'h4);
|
assign pre_pwm = (wb_addr[4: 1]== 4'h4);
|
| Line 346... |
Line 371... |
// zip_sel is not on the bus at this point
|
// zip_sel is not on the bus at this point
|
assign mem_sel =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
|
assign mem_sel =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
|
assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
|
assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
|
assign sdcard_sel=1'b0;
|
assign sdcard_sel=1'b0;
|
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
|
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
|
`else
|
|
assign iovec = { wb_addr[23],wb_addr[18],wb_addr[15:13] }
|
|
|
|
assign sdram_sel =((wb_cyc)&&(io_vec[4]));
|
|
assign flash_sel =((wb_cyc)&&(io_vec[4:3]==2'b01));
|
|
assign mem_sel =((wb_cyc)&&(io_vec[4:0]==5'h07));
|
|
assign cfg_sel =((wb_cyc)&&(io_vec[4:0]==5'h06));
|
|
assign sdcard_sel=((wb_cyc)&&(io_vec[4:0]==5'h05));
|
|
assign scop_sel =((wb_cyc)&&(io_vec[4:0]==5'h04));
|
|
assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
|
|
assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
|
|
assign puf_sel =((wb_cyc)&&(io_vec[4:0]==5'h02));
|
|
assign io_sel =((wb_cyc)&&(io_vec[4:0]==5'h01));
|
|
assign wb_err =((wb_cyc)&&(io_vec[4:0]==5'h00));
|
|
assign flctl_sel = (puf_sel)&&(wb_addr[2]);
|
|
assign pwm_sel = (puf_sel)&&(wb_addr[2:1]==2'b01);
|
|
assign sdcard_sel=1'b0;//((wb_cyc)&&({wb_addr[23],wb_addr[18]}==2'b01));
|
|
`endif
|
|
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(~
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(~
|
(io_sel
|
(io_sel
|
||uart_sel
|
||uart_sel
|
||pwm_sel
|
||pwm_sel
|
| Line 440... |
Line 447... |
uart_rx_int, uart_tx_int);
|
uart_rx_int, uart_tx_int);
|
|
|
//
|
//
|
// PWM (audio) device
|
// PWM (audio) device
|
//
|
//
|
wbpwmaudio pwmdev(i_clk,
|
// The audio rate is given by the number of clock ticks between
|
|
// samples. If we are running at 80 MHz, then divide that by the
|
|
// sample rate to get the first parameter for the PWM device. The
|
|
// second parameter is zero or one, indicating whether or not the
|
|
// audio rate can be adjusted (1), or whether it is fixed within the
|
|
// build (0).
|
|
`ifdef XULA25
|
|
wbpwmaudio #(32'd1814,1) // 44.1 kHz, user adjustable
|
|
`else
|
|
wbpwmaudio #(32'h10000,0) // 8 kHz, fixed audio rate
|
|
`endif
|
|
pwmdev(i_clk,
|
wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
|
wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
|
wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
|
wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
|
|
|
|
|
|
|
//
|
//
|
// FLASH MEMORY CONFIGURATION ACCESS
|
// FLASH MEMORY CONFIGURATION ACCESS
|
//
|
//
|
wire flash_cs_n, flash_sck, flash_mosi;
|
wire flash_cs_n, flash_sck, flash_mosi;
|
`ifdef FLASH_ACCESS
|
`ifdef FLASH_ACCESS
|
| Line 579... |
Line 598... |
// WISHBONE SCOPES
|
// WISHBONE SCOPES
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
`ifdef FLASH_SCOPE
|
|
reg [31:0] r_flash_debug, last_flash_debug;
|
|
wire [31:0] scop_flash_data;
|
wire [31:0] scop_flash_data;
|
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
|
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
|
|
|
|
`ifndef FLASH_ACCESS
|
|
`ifdef FLASH_SCOPE
|
|
`undef FLASH_SCOPE // FLASH_SCOPE only makes sense if you have flash access
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef FLASH_SCOPE
|
|
reg [31:0] r_flash_debug, last_flash_debug;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_flash_debug <= flash_debug;
|
r_flash_debug <= flash_debug;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
last_flash_debug <= r_flash_debug;
|
last_flash_debug <= r_flash_debug;
|
wbscope spiscope(i_clk, 1'b1, (~o_spi_cs_n), r_flash_debug,
|
wbscope spiscope(i_clk, 1'b1, (~o_spi_cs_n), r_flash_debug,
|
| Line 594... |
Line 620... |
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_interrupt);
|
scop_flash_interrupt);
|
`else
|
`else
|
wire [31:0] scop_flash_data;
|
`ifdef WBUS_SCOPE
|
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
|
wbscopc #(5'ha) wbuscope(i_clk, 1'b1, wbus_debug[31], wbus_debug[30:0],
|
|
// Wishbone interface
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
|
wb_data,
|
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
|
scop_flash_interrupt);
|
|
`else
|
assign scop_flash_data = 32'h00;
|
assign scop_flash_data = 32'h00;
|
assign scop_flash_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00);
|
assign scop_flash_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00);
|
assign scop_flash_stall = 1'b0;
|
assign scop_flash_stall = 1'b0;
|
assign scop_flash_interrupt = 1'b0;
|
assign scop_flash_interrupt = 1'b0;
|
`endif
|
`endif
|
|
`endif
|
|
|
|
|
wire [31:0] scop_cfg_data;
|
wire [31:0] scop_cfg_data;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
`ifdef CFG_SCOPE
|
`ifdef CFG_SCOPE
|
| Line 625... |
Line 658... |
|
|
wire [31:0] scop_ram_data;
|
wire [31:0] scop_ram_data;
|
wire scop_ram_ack, scop_ram_stall, scop_ram_interrupt;
|
wire scop_ram_ack, scop_ram_stall, scop_ram_interrupt;
|
`ifdef SDRAM_SCOPE
|
`ifdef SDRAM_SCOPE
|
wire sdram_trigger;
|
wire sdram_trigger;
|
assign sdram_trigger = sdram_sel;
|
assign sdram_trigger = sdram_debug[18]; // sdram_sel;
|
// assign sdram_trigger = ((wbu_cyc)&&(wbu_zip_sel)&&(wbu_stb)&&(~wbu_addr[0])),
|
|
wire sdram_write;
|
|
assign sdram_write = ((wb_cyc)&&(sdram_sel)&&(wb_stb)&&(wb_we)&&(~sdram_stall));
|
|
/*
|
|
reg r_trigger;
|
|
reg [31:0] last_data;
|
|
always @(posedge i_clk)
|
|
if (sdram_write)
|
|
last_data <= wb_data;
|
|
initial r_trigger = 1'b0;
|
|
always @(posedge i_clk)
|
|
if ((sdram_write)&&(last_data == wb_data))
|
|
r_trigger <= 1'b1;
|
|
else
|
|
r_trigger <= 1'b0;
|
|
*/
|
|
|
|
wbscope #(5'ha) sdramscope(i_clk, 1'b1, sdram_trigger,
|
wbscope #(5'hb) sdramscope(i_clk, 1'b1, sdram_trigger,
|
sdram_debug,
|
sdram_debug,
|
// zip_debug,
|
//{ sdram_trigger, wb_data[30:0] },
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
scop_ram_ack, scop_ram_stall, scop_ram_data,
|
scop_ram_ack, scop_ram_stall, scop_ram_data,
|
scop_ram_interrupt);
|
scop_ram_interrupt);
|
