URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
[/] [xulalx25soc/] [trunk/] [rtl/] [busmaster.v] - Diff between revs 2 and 6
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 6 |
| Line 113... |
Line 113... |
wire [31:0] wbu_idata;
|
wire [31:0] wbu_idata;
|
// And then headed back home
|
// And then headed back home
|
wire w_interrupt;
|
wire w_interrupt;
|
// Oh, and the debug control for the ZIP CPU
|
// Oh, and the debug control for the ZIP CPU
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[31: 1]== 31'h083));
|
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]);
|
wire [31:0] zip_dbg_data;
|
wire [31:0] zip_dbg_data;
|
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
|
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
`ifdef INCLUDE_ZIPCPU
|
`ifdef INCLUDE_ZIPCPU
|
((~wbu_zip_sel)&&(wbu_ack))
|
((~wbu_zip_sel)&&(wbu_ack))
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.