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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// Input/master bus
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// Input/master bus
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [(AW-1):0] i_wb_addr;
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input [(AW-1):0] i_wb_addr;
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input [(DW-1):0] i_wb_data;
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input [(DW-1):0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output reg o_wb_stall;
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output reg [(DW-1):0] o_wb_data;
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output reg [(DW-1):0] o_wb_data;
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output wire o_wb_err;
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output reg o_wb_err;
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// Delayed bus
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// Delayed bus
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output reg o_dly_cyc, o_dly_stb, o_dly_we;
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output reg o_dly_cyc, o_dly_we;
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output wire o_dly_stb;
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output reg [(AW-1):0] o_dly_addr;
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output reg [(AW-1):0] o_dly_addr;
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output reg [(DW-1):0] o_dly_data;
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output reg [(DW-1):0] o_dly_data;
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input i_dly_ack;
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input i_dly_ack;
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input i_dly_stall;
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input i_dly_stall;
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input [(DW-1):0] i_dly_data;
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input [(DW-1):0] i_dly_data;
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input i_dly_err;
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input i_dly_err;
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reg loaded;
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initial o_dly_cyc = 1'b0;
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initial o_dly_cyc = 1'b0;
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initial o_dly_stb = 1'b0;
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initial loaded = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_dly_cyc <= i_wb_cyc;
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o_wb_stall <= (loaded)&&(i_dly_stall);
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initial o_dly_cyc = 1'b0;
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always @(posedge i_clk)
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o_dly_cyc <= (i_wb_cyc);
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// Add the i_wb_cyc criteria here, so we can simplify the o_wb_stall
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// Add the i_wb_cyc criteria here, so we can simplify the o_wb_stall
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// criteria below, which would otherwise *and* these two.
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// criteria below, which would otherwise *and* these two.
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_stall)
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loaded <= (i_wb_stb)||((loaded)&&(i_dly_stall)&&(~i_dly_err)&&(i_wb_cyc));
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o_dly_stb <= ((i_wb_cyc)&&(i_wb_stb));
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assign o_dly_stb = loaded;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_stall)
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if (~i_dly_stall)
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o_dly_we <= i_wb_we;
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o_dly_we <= i_wb_we;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_stall)
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if (~i_dly_stall)
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o_dly_addr<= i_wb_addr;
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o_dly_addr<= i_wb_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_stall)
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if (~i_dly_stall)
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o_dly_data <= i_wb_data;
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o_dly_data <= i_wb_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
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o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_data <= i_dly_data;
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o_wb_data <= i_dly_data;
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// Our only non-delayed line, yet still really delayed. Perhaps
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always @(posedge i_clk)
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// there's a way to register this?
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o_wb_err <= (i_dly_err)&&(o_dly_cyc)&&(i_wb_cyc);
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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// assign o_wb_stall=((i_wb_cyc)&&(i_dly_stall)&&(o_dly_stb));//&&o_cyc
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assign o_wb_stall = ((i_dly_stall)&&(o_dly_stb));//&&o_cyc
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assign o_wb_err = i_dly_err;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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