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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// includes the multiply. (This parameter may still be overridden, as with
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// includes the multiply. (This parameter may still be overridden, as with
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// any parameter ...) If the multiply is not included and
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// any parameter ...) If the multiply is not included and
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// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
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// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
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// instruction that will then trip the illegal instruction trap.
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// instruction that will then trip the illegal instruction trap.
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//
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//
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// Either not defining this value, or defining it to zero will disable the
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// hardware multiply. A value of '1' will cause the multiply to occurr in one
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// clock cycle only--often at the expense of the rest of the CPUs speed.
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// A value of 2 will cause the multiply to have a single delay cycle, 3 will
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// have two delay cycles, and 4 (or more) will have 3 delay cycles.
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//
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//
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`define OPT_MULTIPLY 2
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`define OPT_MULTIPLY 4
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//
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//
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//
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//
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//
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//
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// OPT_DIVIDE controls whether or not the divide instruction is built and
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// OPT_DIVIDE controls whether or not the divide instruction is built and
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// included into the ZipCPU by default. Set this option and a parameter will
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// included into the ZipCPU by default. Set this option and a parameter will
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//
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//
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// `define OPT_IMPLEMENT_FPU
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// `define OPT_IMPLEMENT_FPU
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//
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//
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//
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//
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//
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//
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// OPT_NEW_INSTRUCTION_SET controls whether or not the new instruction set
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// is in use. The new instruction set contains space for floating point
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// operations, signed and unsigned divide instructions, as well as bit reversal
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// and ... at least two other operations yet to be defined. The decoder alone
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// uses about 70 fewer LUTs, although in practice this works out to 12 fewer
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// when all works out in the wash. Further, floating point and divide
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// instructions will cause an illegal instruction exception if they are not
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// implemented--so software capability can be built to use these instructions
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// immediately, even if the hardware is not yet ready.
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//
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// This option is likely to go away in the future, obsoleting the previous
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// instruction set, so I recommend setting this option and switching to the
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// new instruction set as soon as possible.
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//
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`define OPT_NEW_INSTRUCTION_SET
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//
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//
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//
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//
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//
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//
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//
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// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and
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// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and
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// whether or not it can issue one instruction per clock. When set, the
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// whether or not it can issue one instruction per clock. When set, the
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// prefetch has no cache, and only one instruction is fetched at a time.
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// prefetch has no cache, and only one instruction is fetched at a time.
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// This effectively sets the CPU so that only one instruction is ever
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// This effectively sets the CPU so that only one instruction is ever
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//
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//
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`define OPT_PIPELINED_BUS_ACCESS
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`define OPT_PIPELINED_BUS_ACCESS
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//
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//
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//
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//
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//
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//
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`ifdef OPT_NEW_INSTRUCTION_SET
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//
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//
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//
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//
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//
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// The new instruction set also defines a set of very long instruction words.
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// The new instruction set also defines a set of very long instruction words.
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// Well, calling them "very long" instruction words is probably a misnomer,
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// Well, calling them "very long" instruction words is probably a misnomer,
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// although we're going to do it. They're really 2x16-bit instructions---
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// although we're going to do it. They're really 2x16-bit instructions---
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// simulator all need to be updated as well ....
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// simulator all need to be updated as well ....
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//
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//
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`define OPT_VLIW
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`define OPT_VLIW
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//
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//
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//
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//
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`endif // OPT_NEW_INSTRUCTION_SET
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//
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//
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//
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`endif // OPT_SINGLE_FETCH
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`endif // OPT_SINGLE_FETCH
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//
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//
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//
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//
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//
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//
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