| Line 51... |
Line 51... |
assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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wire [31:0] w_rol_result;
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wire [31:0] w_rol_result;
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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// Shift register pre-logic
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// Shift register pre-logic
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wire [32:0] w_lsr_result, w_asr_result;
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wire [32:0] w_lsr_result, w_asr_result, w_lsl_result;
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wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted;
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assign w_pre_asr_input = { i_a, 1'b0 };
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assign w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
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: w_pre_asr_shifted;// ASR
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assign w_lsr_result = (|i_b[31:5])? 33'h00
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assign w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
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:((i_b[5])?{32'h0,i_a[31]}
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: ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
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assign w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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:((i_b[5])?{i_a[0], 32'h0}
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: ({1'b0, i_a } << i_b[4:0])); // LSL
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// Bit reversal pre-logic
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// Bit reversal pre-logic
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wire [31:0] w_brev_result;
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wire [31:0] w_brev_result;
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genvar k;
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genvar k;
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generate
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generate
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| Line 114... |
Line 122... |
4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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`ifndef LONG_MPY
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`ifndef LONG_MPY
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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`endif
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`endif
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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| Line 294... |
Line 302... |
4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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`ifdef LONG_MPY
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`ifdef LONG_MPY
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4'b1000: o_c <= r_mpy_result[31:0]; // MPY
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4'b1000: o_c <= r_mpy_result[31:0]; // MPY
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`else
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`else
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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