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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [cpuops.v] - Diff between revs 21 and 46
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| Rev 21 |
Rev 46 |
| Line 94... |
Line 94... |
// A 4-way multiplexer can be done in one 6-LUT.
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// the Xilinx multiplexer fabric that follows.
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// the Xilinx multiplexer fabric that follows.
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// this will cost a minimum of 132 6-LUTs.
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// this will cost a minimum of 132 6-LUTs.
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wire w_illegal;
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generate
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generate
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if (IMPLEMENT_MPY == 0)
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if (IMPLEMENT_MPY == 0)
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begin
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begin
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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| Line 124... |
Line 125... |
endcase
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endcase
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end
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end
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assign o_busy = 1'b0;
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assign o_busy = 1'b0;
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assign w_illegal = (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
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reg r_illegal;
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reg r_illegal;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
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r_illegal <= w_illegal;
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assign o_illegal = r_illegal;
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assign o_illegal = r_illegal;
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end else begin
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end else begin
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//
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//
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// Multiply pre-logic
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// Multiply pre-logic
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//
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//
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| Line 179... |
Line 181... |
r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
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r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
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&&(i_op[3:1] == 3'h5);
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&&(i_op[3:1] == 3'h5);
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assign o_busy = r_busy;
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assign o_busy = r_busy;
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assign w_illegal = 1'b0;
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assign o_illegal = 1'b0;
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assign o_illegal = 1'b0;
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end endgenerate
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end endgenerate
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assign z = (o_c == 32'h0000);
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assign z = (o_c == 32'h0000);
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assign n = (o_c[31]);
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assign n = (o_c[31]);
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| Line 193... |
Line 196... |
initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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else
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else
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o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)
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o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)&&(~w_illegal)
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||(o_busy);
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||(o_busy);
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endmodule
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endmodule
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