| Line 42... |
Line 42... |
// Output parameters
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// Output parameters
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output reg o_busy, o_valid, o_err;
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output reg o_busy, o_valid, o_err;
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output reg [(BW-1):0] o_quotient;
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output reg [(BW-1):0] o_quotient;
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output wire [3:0] o_flags;
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output wire [3:0] o_flags;
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// r_busy is an internal busy register. It will clear one clock
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// before we are valid, so it can't be o_busy ...
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//
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reg r_busy;
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reg [(2*BW-2):0] r_divisor;
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reg [(2*BW-2):0] r_divisor;
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reg [(BW-1):0] r_dividend;
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reg [(BW-1):0] r_dividend;
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wire [(BW):0] diff; // , xdiff[(BW-1):0];
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wire [(BW):0] diff; // , xdiff[(BW-1):0];
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assign diff = r_dividend - r_divisor[(BW-1):0];
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assign diff = r_dividend - r_divisor[(BW-1):0];
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// assign xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
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// assign xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
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reg r_sign, pre_sign, r_z, r_c;
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reg r_sign, pre_sign, r_z, r_c, last_bit;
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reg [(LGBW):0] r_bit;
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reg [(LGBW-1):0] r_bit;
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initial r_busy = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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r_busy <= 1'b0;
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else if (i_wr)
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r_busy <= 1'b1;
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else if ((last_bit)||(o_err))
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r_busy <= 1'b0;
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initial o_busy = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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o_busy <= 1'b0;
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o_busy <= 1'b0;
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end else if (i_wr)
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else if (i_wr)
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begin
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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end else if ((o_busy)&&((r_bit == 6'h0)||(o_err)))
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else if (((last_bit)||(o_err))&&(~r_sign))
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o_busy <= 1'b0;
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else if (~r_busy)
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o_busy <= 1'b0;
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o_busy <= 1'b0;
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// else busy is zero and stays at zero
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_wr))
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if ((i_rst)||(i_wr))
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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else if (o_busy)
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else if (r_busy)
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begin
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begin
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if ((r_bit == 6'h0)||(o_err))
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if ((last_bit)||(o_err))
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o_valid <= (o_err)||(~r_sign);
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o_valid <= (o_err)||(~r_sign);
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end else if (r_sign)
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end else if (r_sign)
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begin
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begin
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// if (o_err), o_valid is already one.
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// if (o_err), o_valid is already one.
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// if not, o_valid has not yet become one.
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// if not, o_valid has not yet become one.
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| Line 83... |
Line 96... |
if((i_rst)||(o_valid))
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if((i_rst)||(o_valid))
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o_err <= 1'b0;
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o_err <= 1'b0;
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else if (o_busy)
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else if (o_busy)
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o_err <= (r_divisor == 0);
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o_err <= (r_divisor == 0);
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initial last_bit = 1'b0;
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always @(posedge i_clk)
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if ((i_wr)||(pre_sign)||(i_rst))
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last_bit <= 1'b0;
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else if (r_busy)
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last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1});
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always @(posedge i_clk)
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always @(posedge i_clk)
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// if (i_rst) r_busy <= 1'b0;
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// else
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if (i_wr)
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if (i_wr)
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begin
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begin
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//
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// Set our values upon an initial command. Here's
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// where we come in and start.
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//
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// r_busy <= 1'b1;
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//
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o_quotient <= 0;
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o_quotient <= 0;
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// r_bit <= { 1'b1, {(LGBW){1'b0}} };
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r_bit <= {(LGBW){1'b1}};
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r_bit <= { 1'b0, {(LGBW){1'b1}} };
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r_divisor <= { i_denominator, {(BW-1){1'b0}} };
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r_divisor <= { i_denominator, {(BW-1){1'b0}} };
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r_dividend <= i_numerator;
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r_dividend <= i_numerator;
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r_sign <= 1'b0;
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r_sign <= 1'b0;
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pre_sign <= i_signed;
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pre_sign <= i_signed;
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r_z <= 1'b1;
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r_z <= 1'b1;
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end else if (pre_sign)
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end else if (pre_sign)
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begin
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begin
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// r_bit <= r_bit - 1;
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//
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r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));;
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// Note that we only come in here, for one clock, if
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// our initial value may have been signed. If we are
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// doing an unsigned divide, we then skip this step.
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//
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r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));
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// Negate our dividend if necessary so that it becomes
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// a magnitude only value
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if (r_dividend[BW-1])
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if (r_dividend[BW-1])
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r_dividend <= -r_dividend;
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r_dividend <= -r_dividend;
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// Do the same with the divisor--rendering it into
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// a magnitude only.
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if (r_divisor[(2*BW-2)])
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if (r_divisor[(2*BW-2)])
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r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)];
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r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)];
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//
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// We only do this stage for a single clock, so go on
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// with the rest of the divide otherwise.
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pre_sign <= 1'b0;
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pre_sign <= 1'b0;
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end else if (o_busy)
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end else if (r_busy)
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begin
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begin
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r_bit <= r_bit + {(LGBW+1){1'b1}}; // r_bit = r_bit - 1;
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// While the divide is taking place, we examine each bit
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// in turn here.
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//
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r_bit <= r_bit + {(LGBW){1'b1}}; // r_bit = r_bit - 1;
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r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
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r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
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if (|r_divisor[(2*BW-2):(BW)])
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if (|r_divisor[(2*BW-2):(BW)])
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begin
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begin
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end else if (diff[BW])
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end else if (diff[BW])
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begin
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begin
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//
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// diff = r_dividend - r_divisor[(BW-1):0];
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//
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// If this value was negative, there wasn't
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// enough value in the dividend to support
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// pulling off a bit. We'll move down a bit
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// therefore and try again.
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//
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end else begin
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end else begin
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//
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// Put a '1' into our output accumulator.
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// Subtract the divisor from the dividend,
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// and then move on to the next bit
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//
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r_dividend <= diff[(BW-1):0];
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r_dividend <= diff[(BW-1):0];
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o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
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o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
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r_z <= 1'b0;
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r_z <= 1'b0;
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end
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end
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end else if (r_sign)
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end else if (r_sign)
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| Line 125... |
Line 179... |
end
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end
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// Set Carry on an exact divide
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// Set Carry on an exact divide
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wire w_n;
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wire w_n;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_c <= (o_busy)&&((diff == 0)||(r_dividend == 0));
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r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0));
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assign w_n = o_quotient[(BW-1)];
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assign w_n = o_quotient[(BW-1)];
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assign o_flags = { 1'b0, w_n, r_c, r_z };
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assign o_flags = { 1'b0, w_n, r_c, r_z };
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endmodule
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endmodule
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