| Line 87... |
Line 87... |
wire [(AW-1):0] o_dcd_branch_pc;
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wire [(AW-1):0] o_dcd_branch_pc;
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reg o_dcdI, o_dcdIz;
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reg o_dcdI, o_dcdIz;
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wire [4:0] w_op;
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wire [4:0] w_op;
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wire w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU;
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wire w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU, w_brev;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire [3:0] w_cond;
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wire [3:0] w_cond;
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| Line 121... |
Line 121... |
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assign w_op= iword[26:22];
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assign w_op= iword[26:22];
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assign w_mov = (w_op == 5'h0f);
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assign w_mov = (w_op == 5'h0f);
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assign w_ldi = (w_op[4:1] == 4'hb);
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assign w_ldi = (w_op[4:1] == 4'hb);
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assign w_brev = (w_op == 5'hc);
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assign w_cmptst = (w_op[4:1] == 4'h8);
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assign w_cmptst = (w_op[4:1] == 4'h8);
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assign w_ldixx = (w_op[4:1] == 4'h4);
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assign w_ldixx = (w_op[4:1] == 4'h4);
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assign w_ALU = (~w_op[4]);
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assign w_ALU = (~w_op[4]);
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// 4 LUTs
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// 4 LUTs
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| Line 187... |
Line 188... |
//
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//
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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// and writes to the PC/CC register(s).
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// and writes to the PC/CC register(s).
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assign w_wF = (w_cmptst)
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assign w_wF = (w_cmptst)
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||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
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||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
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||((w_ALU)&&(~w_mov)&&(~w_ldixx)
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||((w_ALU)&&(~w_mov)&&(~w_ldixx)&&(~w_brev)
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&&(iword[30:28] != 3'h7))));
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&&(iword[30:28] != 3'h7))));
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// Bottom 13 bits: no LUT's
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// Bottom 13 bits: no LUT's
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// w_dcd[12: 0] -- no LUTs
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// w_dcd[12: 0] -- no LUTs
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// w_dcd[ 13] -- 2 LUTs
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// w_dcd[ 13] -- 2 LUTs
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| Line 414... |
Line 415... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
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o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
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&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
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&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
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&&(i_instruction[17:14] == o_dcdB[3:0])
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&&(i_instruction[17:14] == o_dcdB[3:0])
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&&(i_instruction[17:14] != o_dcdA[3:0])
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&&(i_gie == o_gie)
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&&(i_gie == o_gie)
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&&((i_instruction[21:19]==o_cond[2:0])
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&&((i_instruction[21:19]==o_cond[2:0])
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||(o_cond[2:0] == 3'h0))
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||(o_cond[2:0] == 3'h0))
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&&((i_instruction[13:0]==r_I[13:0])
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&&((i_instruction[13:0]==r_I[13:0])
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||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
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||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
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