URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [idecode.v] - Diff between revs 62 and 86

Rev 62	Rev 86
Line 86...	Line 86...
`wire dcdA_stall, dcdB_stall, dcdF_stall;`	`wire dcdA_stall, dcdB_stall, dcdF_stall;`
`wire o_dcd_early_branch;`	`wire o_dcd_early_branch;`
`wire [(AW-1):0] o_dcd_branch_pc;`	`wire [(AW-1):0] o_dcd_branch_pc;`
`reg o_dcdI, o_dcdIz;`	`reg o_dcdI, o_dcdIz;`
`ifdef OPT_PIPELINED	`ifdef OPT_PIPELINED
`reg r_lock, r_pipe;`	`reg r_lock;`
	`endif
	`ifdef OPT_PIPELINED_BUS_ACCESS
	`reg r_pipe;`
`endif	`endif


`wire [4:0] w_op;`	`wire [4:0] w_op;`
`wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;`	`wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;`
Line 441...	Line 444...
`// by one`	`// by one`
`// Note that we're not using iword here ... there's a lot of logic`	`// Note that we're not using iword here ... there's a lot of logic`
`// taking place, and it's only valid if the new word is not compressed.`	`// taking place, and it's only valid if the new word is not compressed.`
`//`	`//`
`reg r_valid;`	`reg r_valid;`
`ifdef OPT_PIPELINED	`ifdef OPT_PIPELINED_BUS_ACCESS
`initial r_pipe = 1'b0;`	`initial r_pipe = 1'b0;`
`always @(posedge i_clk)`	`always @(posedge i_clk)`
`if (i_ce)`	`if (i_ce)`
`r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])`	`r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])`
`&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])`	`&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])`